JPS5818699A - Voice coder - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a voice encoding device, and particularly to a voice encoding device that can realize miniaturization of the entire device and is suitable for a message clock or the like.

Recently, a message clock is being considered that not only uses a wristwatch or the like as a time indicating means, but also allows a message to be input by voice and the input message to be output by voice. The message hour hand incorporating this type of message mechanism is rounded, and its main purpose is to be used as a watch, for example, a wristwatch, and the size of the message mechanism must necessarily be limited.

By the way, in general, as a voice encoding method in a voice storage system that encodes one voice input/signal and stores it as voice information, and decodes the stored voice information and outputs it as voice, the A-meter synthesis method such as PA QOR is used. The audio encoding method used is known. However, this type of audio encoding method requires an extremely large amount of calculation processing, so a high-speed and large-scale combinator is required for real-time processing. Therefore, it is difficult to apply it to devices such as message clocks that require small size devices. For these reasons, the ADPCM (Adaptive Differential Pulse Modulation) method, which has relatively low information compression efficiency but requires a relatively small device as a whole, is the most suitable audio encoding method for this type of message clock. It has come to be recognized that there is. However, AD
The PCM method converts an input sample value into a PCM code, calculates the difference value between the current sample value and the previous sample value by digital calculation processing, and sets the quantization step width as a function of the digital difference value. Mu/D
High-speed and large-scale conversion circuits, arithmetic units, etc. were required, and the entire device had to be relatively large. The purpose of this invention is to provide a voice encoding device suitable for message clocks and the like. Rounding The audio encoding device according to the present invention is an audio encoding device that encodes an audio input signal at a predetermined sampling period. Successive approximation 1 [A/D' conversion circuit and the above-mentioned] which sequentially compares the difference value analog quantity and the reference analog quantity whose level value changes stepwise and converts the said difference value analog quantity into the corresponding difference value digital information. It is equipped with a quantization step width setting circuit that selects the quantization step width of the reference analog quantity, and the wrinkle quantization step width setting circuit is based on the difference value digital information and quantization step width digital information in the previous encoding process. ◇The present invention will be described below with reference to the drawings.

Figure 111 shows the configuration of an embodiment of a speech encoding device according to the present invention.

In FIG. 1, a difference value calculation circuit (1) performs analog calculation processing on an input audio input signal and outputs a difference value analogue amount (a). Successive approximation 111 A/D conversion circuit (ori) O difference value analog quantity (
A) is successively compared in size with the reference analog quantity (b), and the difference value analog quantity (&) is calculated as the corresponding difference value digital information II.
Convert to (@). Todoroki performs the A/D conversion process), quantization step width setting circuit (successive approximation/D
A process is performed to select the quantization step width of the reference anarchic quantity to be input to one input terminal of the comparator (4) of the conversion circuit. That is, the quantization step width setting circuit (
3), as described later, is the difference value digital information used in the current encoding process←) and the quantization step width digital information (based on the quantization step width that should be set in the current encoding process) is selected so that the difference value digital information (e) does not have large variations between each encoding process.

In this way, the round lid portion value digital information elf (e) h converted by the successive approximation section M/D conversion circuit (3) K is stored in a storage section (not shown), and read out from the storage section as appropriate. The 0 blue voice input Confucian code, which explains the processing operation below 0, is decoded by the decoding device) and output as audio.
Thai scolding pulse redemption (f) from Hentsuta 1111m)
Ksynchronized with the first sample and hold circuit (7) KsI
− This time, the analog sample value (
b). At this point, the second sample and hold circuit (8) has already generated the sampling pulse (J) from the ring kakunta (b), which is a point in time that has gone back by the delay time caused by the slow arc circuit (. The analog sample value of the hold circuit (7), that is, the previous analog sample value (transfer) is shifted and held. This analog sample value (b) of the first sample hold circuit (7) and the second sample hold circuit (8)
) is the previous analog sample value (b) of the switching circuit (9)
The difference value analog quantity (a) is inputted to the subtracter QO through the subtracter QO, and the difference value analog quantity (a) expressed as an absolute value is calculated in the subtracter QO. and previous analog sample value (6)
Of these, the one with the larger value is input, and the one side input terminal of the subtractor 0Φ receives both analog sample values (billions) and (b).
The one with the smaller value is input.0 This input pattern determination is performed by selecting the switching pattern of the switching circuit @) based on the magnitude comparison result by the comparator (c). The differential value analog quantity (a) from is held as an input to one long terminal of the comparator (4) of the successive approximation cover/D converter circuit a), and is input to the other long terminal of the comparator (4). The level value is successively compared with the standard analogue quantity (the level value increases stepwise). This reference analog (reg) is registered until the time when the logic rlJ signal is output from the comparator (4), that is, until the reference analog l-)O level value exceeds the level value of the difference value analog l-). In synchronization with the content update timing of (2), the quantization step width setting circuit (1) K is given in a stepped waveform as shown in Figure 2, which increases successively by the selected quantization step width value. It will be done.

1F211K>-, the horizontal axis is a digital value corresponding to the contents of the register (b) that are updated sequentially, and the vertical axis is the output voltage value at the points shown in Figures 1 and 2, that is, the level value of the reference analog quantity. If the equivalent resistance 2 of the waveform (a) Fi 11th country D/mu conversion link is 2-1, then 2 is Z
-R, the reference analog quantity waveform and waveform (C) respectively represent the reference analog quantity waveform when the above-mentioned equivalent resistance 2 is Z=R/4. These reference analog pg quantity waveforms (
The quantization step width Δ in a), (c), and (c) is determined as follows. That is, the resistance ladder circuit shown in FIG. 1, the output pattern information of the register (2), and the D/mu conversion circuit (to) of the quantization step width setting H path (3) are expressed as an equivalent circuit as shown in FIG. K>-, the impedance of the resistance ladder circuit viewed from terminal A in the figure is always R if the power supply E is a constant voltage power supply with an internal resistance of 0.
The output voltage is determined by the voltage division ratio between the impedance R and the equivalent impedance 2 of the D/mu conversion circuit. Equivalent impedance 2 is! The output pattern information corresponds to the output pattern information of -), and the pattern pattern information is ``rooo'', ``rool'', and ``rolo''.

roll'', rlooJ, rlolJ, rllOJ, r
lllJ, the equivalent impedance 2 is "-" respectively.
.

rRJ rR/2J, r'B/! iJ, l/
4J, 115J, l/ajerR/'IJ. Therefore, if the quantization step width is 1 when the equivalent impedance 2 is one ring, then the quantization step width Δj (J
-0,1,2,! 1, 4, 5.

@,? )dΔ1mΔ·/(1+J).

When the level value of the reference analog l-) as described above exceeds the level value of the difference value anag amount (mouth), the wIIl "1" signal is output from comparison 1) (4) &J), The selector is reset by the H4rIJ signal, and the subsequent update contents of the ringing counter are no longer set in the register. That is, the contents of the register so are kept fixed until the next rtao encoding process is started, and the contents of the register are stored as differential value digital information (a) in a storage section (not shown). At this time, positive/negative indication information (1) from the comparator section of the difference value calculation circuit (1) is also stored.

Here, the quantization step width is quantization step @
Setting circuit (2) K) is selected. That is, prior to the current encoding process, the quantization step width digital information (φ, that is, the !multiplexer output pattern information set in the previous encoding process) is stored at the time when the current encoding process is started, that is, the ring counter ( mouth) to the numbering pulse (j
) is displayed, it is set in the register @ as memory access address information, and the first ROM @ and the second
The ROM of 1 is accessed according to the address information.

The quantization step width digital information is read from the corresponding data storage address of the rounded lOR0M so and the same data storage address of the second ROM so. Here, the round quantization step width digital information pre-stored in the first ROM@ and other quantization step width digital information pre-stored in the second ROM@ are as shown in Tables 1 and 2, for example. Become a kimono. Note that the numerical values in Table 1 and the second *Ksi- correspond to the above-mentioned formula 9, Δj=Δ·/(1+J)Ksi-J9.

Table 1 Table 2 As is clear from Table 1 and Table 2, jlIO
Since the KOMOI40 stored data has a smaller value compared to the access address information, that is, So1 encoding II & quantization step width digital information (2), it is now 1Ill.
It can be considered as an increase ROM that increases the quantization step width during lI encoding processing, and the ROMm at the end chain 2 is different from the first ROMQII above). Transformation! & It can be considered a reduction ROM in the sense that it is set smaller than the quantization step width during communication. In this way, the ROMrI4 and the second ROM
Each quantization step width digital information respectively read from Zeng is,! Luchipreque? (to), only one of them is selected and output from the D/MU conversion circuit (to) K. This selection process by the multi-preference IJ4 is determined based on the difference value digital information (e) from the previous encoding process. That is, in the case of this embodiment, the difference value digital information (
If the MSB (most significant 〈〈〈〉)) of e) is a logic rQJ, the read information of the second ROMC 1) is passed to the bus in order to reduce the quantization step width in the encoding process, while the above MOB is a logic rQJ. If it is "1" and 9, the ROMMo4 of C11 is used to increase the quantization step width.
The read information is passed. The lock generator (2) advances the contents of the ring counter and instructs to set the select gate.

And from the ring kakunta (ro) to the sampling pa
) is generated, the above-mentioned audio encoding geography is repeated, and the difference value digital rare information (e) and positive/negative indication information (i) are stored bare in a storage unit (not shown). Ru.

As explained above, the present invention includes an audio encoding device KTh that encodes an audio input signal at a predetermined sampling period.
A difference value calculation circuit calculates the analog difference value between the current analog sample value and the previous analog sample value of the audio input signal, and the level value is calculated stepwise with the amount of difference value analization from the difference value calculation circuit. A successive approximation layer A/D conversion circuit that sequentially compares the varying reference analog quantity with the varying reference analog quantity and converts the difference value analog quantity into corresponding difference value digital information and a quantization step width of the reference analog quantity are selected. A quantization step width setting circuit is provided, and the quantization step width setting circuit selects the quantization step width in the current encoding process based on the difference value digital information and the quantization step width digital information in the previous encoding process. It was configured to do so. In other words, the calculation of the difference value and the selection of the quantization step width are performed by the analog signal processing means.

This rounding conventionally requires high speed and large scale M/D.
Since no converter, arithmetic device, etc. are used, the entire device can be made sufficiently compact and inexpensive, making it possible to provide a voice encoding device particularly suitable for message watches.

[Brief explanation of the drawing]

FIG. 1 shows the configuration of an embodiment of a speech encoding device according to the present invention.
FIG. 2 shows a waveform diagram of a reference analog quantity, and FIG. 3 shows an electrical equivalent circuit of the main part in FIG. 1. 1...Difference value calculation circuit 2...Successive approximation type A/D conversion circuit 3 II@11 quantization step width setting circuit a...Difference value analog quantity b...Reference analog quantity gee-difference Value digital information d...Quantization step width Digital information g...This time's analog value h111111 Previous analog number value Agent Patent attorney Tsutomu Adachi Figure 2 01 234567 'II!:, 3 Figure

Claims (1)

[Claims] In an audio encoding device that encodes an audio input signal at a predetermined sampling period, a difference value calculation circuit that calculates an analog difference value between the current analog sample value and the previous analog sample value of the audio input signal, and a scissor difference value calculation A successive approximation system that successively compares the difference value analog quantity from the circuit with a reference analog quantity whose level value changes stepwise and converts the difference value analog quantity into corresponding difference value digital information.
It is equipped with a D conversion circuit and a quantization step width setting circuit that selects the quantization step width of the reference analog quantity. A speech encoding device 0 characterized in that it is configured to select a quantization step width in the encoding process.