JPS58184735A - Integrated circuit chip - Google Patents
Integrated circuit chipInfo
- Publication number
- JPS58184735A JPS58184735A JP57067973A JP6797382A JPS58184735A JP S58184735 A JPS58184735 A JP S58184735A JP 57067973 A JP57067973 A JP 57067973A JP 6797382 A JP6797382 A JP 6797382A JP S58184735 A JPS58184735 A JP S58184735A
- Authority
- JP
- Japan
- Prior art keywords
- chip
- chips
- bonding pads
- integrated circuit
- mutually facing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/156—Material
- H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
- H01L2924/15787—Ceramics, e.g. crystalline carbides, nitrides or oxides
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Semiconductor Integrated Circuits (AREA)
- Wire Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
〔技術分野〕
本発明は、チップを実装する際に用いるボッディングパ
ッドに改良１ｉニアＩＯえた集積回路チップに関し、特
にメモリ集積回路チップに有効なものである。DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to an integrated circuit chip having an improved 1i near IO on a boding pad used when mounting the chip, and is particularly effective for memory integrated circuit chips.
近年、コンピュータ等に使用されるメモリ装置の大谷首
化に伴ない、メモリチップの高密度ｌｌ装の必要性がＡ
ｉまっている。In recent years, with the increasing demand for memory devices used in computers, etc., the need for high-density packaging of memory chips has increased.
I'm waiting.
従来のチップの＾密度実装の方法としては、夕１図に示
すようにセラミック基板１の上面に複数のチップ２を載
設し、セラきツク基板１の上面に形成したパッド３とチ
ップ２の上面に形成したパッドとをボンディングワイヤ
で接続し、セラミック基板ｌのパッド３間はセラミック
基板上の配線（図示せず）で接続することにより、複数
のチップ２１に接続するものが採用されている。この従
来のチップ高密度実装方法によれば、チップをデュアル
ライノのケースに入れて実装する他の従来方法に較べ確
かに高密度実装がｉ：ｔＴ能となる。The conventional method for high-density mounting of chips is to mount a plurality of chips 2 on the top surface of a ceramic substrate 1, as shown in Figure 1, and connect the pads 3 formed on the top surface of the ceramic substrate 1 with the chips 2. The pads formed on the top surface are connected with bonding wires, and the pads 3 of the ceramic substrate 1 are connected with wiring (not shown) on the ceramic substrate, thereby connecting to a plurality of chips 21. . According to this conventional high-density chip mounting method, compared to other conventional methods in which the chips are mounted in a dual rhino case, high-density mounting is certainly achieved with i:tT performance.
しかし、この従来のチップ高密度実装方法においては、
チップ間の接続をセラミック基板上の配線會介して行な
うため、チップとセラミック基板を結ぶ丸めのポンディ
ングパッドをセラミック基板−ヒに必ず設けなければな
らず、そのポンディングパッド分のスペースだけどうし
ても実装密度を高くすることができないといった欠点が
あり九。However, in this conventional high-density chip mounting method,
Since the connections between chips are made through wiring on the ceramic substrate, round bonding pads must be provided on the ceramic substrate to connect the chips and the ceramic substrate, and the space for the bonding pads must be used for mounting. It has the disadvantage of not being able to increase the density.9.
本発明は上記従来のチップ実装方法の欠点に鑑み、チッ
プの複数の入力信号端子としてそれぞれ二１１！！一対
のポンディングパッドを設け、これら二１１１一対のポ
ンディングパッドをチップ上面の対向する両側辺のほぼ
向き合う位置にそれぞれ一個づつ配置し、チップとチッ
プをそれぞれのチップ上面に設けたポンディングパッド
間で直接ポンディングできるようにして、チップの一層
の高密度実装′Ｊｋ可能ならしめた集積回路チップの開
示を目的とする。In view of the above-mentioned drawbacks of the conventional chip mounting method, the present invention provides a plurality of input signal terminals for each chip. ! A pair of bonding pads are provided, and one pair of these 2111 pair of bonding pads are arranged at substantially opposite positions on opposite sides of the top surface of the chip, and the chips are placed between the bonding pads provided on the top surface of each chip. An object of the present invention is to disclose an integrated circuit chip that can be directly bonded to enable higher density packaging of chips.
講２図及び第３図に示す本発明の一実施例について説明
する。 １■１
第１図は６４にビットダイナミックＲＡＭのチップにお
けるポンディングパッドの配置【示している。一般に、
アドレス２回転送方式の６４１ワード×１ビツト構成の
メモリチップに必要な入力信号すなわちその端子数は、
アドレス信号熾子が８＋ｗｉ、クロック信号熾子が２個
、ライトイネーブル信号熾子が１個、ライトデータ信号
端子が１個の計１２４＠である。その他の膚子としてリ
ードデータ信号、及び電源端子が必要である。第２図の
例では、それぞれの入力信号端子用のポンディングパッ
ドとして、アドレス信号用ポンディングパッドＡｏ−Ａ
ｏ、 ＡＩ −Ｎ１−−−−− 、 Ａ７− Ａ’７、
クロック信号用ポンディングパッドＲＡＳ −ＲＡＳ’
、 ＣＡ８−ω口′、２イトイネ一ブル信号用ポンデ
ィングパッドｗｇ−Ｗｌｌ’のように、二１１！一対の
ポンディングパッド４，４′がチップ２の対向する上面
両側辺に沿ってそれぞれほぼ向き合う位置に配置されて
い・′（、
る。それぞれ一対を成す二個のポンディングパッドはチ
ップ内部で接続されており、いづれのボンティングパッ
ドから信号を供給しても等価となっている。An embodiment of the present invention shown in Figs. 2 and 3 will be described. 1.1 FIG. 1 shows the arrangement of bonding pads on a bit dynamic RAM chip at 64. in general,
The input signals, that is, the number of terminals required for a memory chip with a 641 word x 1 bit configuration using the two-address transfer method, are as follows:
There are 8+wi address signal terminals, 2 clock signal terminals, 1 write enable signal terminal, and 1 write data signal terminal, for a total of 124 @. Other elements required include read data signals and power supply terminals. In the example shown in FIG. 2, address signal bonding pads Ao-A are used as bonding pads for each input signal terminal.
o, AI-N1-----, A7-A'7,
Clock signal bonding pad RAS -RAS'
, CA8-ωmouth', 2-item enable signal pounding pad wg-Wll', 211! A pair of bonding pads 4 and 4' are arranged along both sides of the opposing top surface of the chip 2 at positions that are substantially facing each other.The two bonding pads forming a pair are connected inside the chip. Therefore, the signal is equivalent even if the signal is supplied from either bonding pad.
第３図はこのような本発明によるチップ！を、Ｍ Ｘ
Ｎ ＩＩＩ使用した（ ６４ＫＸＭ ）ワード×Ｎビッ
ト構成のメモリパッケージの実装状態の一部を示す図面
で−ある。このようなメモリパッケージを構成する場会
は、全チップのアドレス信号用、りはツク１６号用、ラ
イトイネーブル信号用の各ボアディングハツトＡＯ−Ａ
’０−−−−−、０Ａ８− ＯＡ８’ Ｗｌ−Ｗｌｌ’
が共通に接続してあり、それぞれ一つのドライバでそれ
らの信号全供給することができる。また、クロック信号
用ボンティングバッドＲム８− ＲＡ８ ’についても
、ワード選択のためＮ個共通に愛続されてＭ９、一つの
ドライバでその信号を供給し動作させることができる。Figure 3 shows such a chip according to the present invention! , M
2 is a diagram showing a part of the mounting state of a memory package using (64KXM) words×N bits using NIII; FIG. When configuring such a memory package, each boreing hat AO-A is used for the address signal of all chips, for Riwatsuk No. 16, and for the write enable signal.
'0-----, 0A8-OA8'Wl-Wll'
are connected in common, and one driver can supply all of their signals. Further, as for the clock signal bonding pads R8-RA8', N pieces are connected in common for word selection, and a single driver can supply the signal and operate the bonding pads M9.
したがって、第３図に示すように複数のチップ２ｔ１そ
の間を（Ｉ！ｔｉにした状態でセラミック基板１上に実
装し、隣接するチップにおける同一信号のボンティング
パッド同士全接続することがで龜る。Therefore, as shown in FIG. 3, it is possible to mount a plurality of chips 2t1 on the ceramic substrate 1 in a state of (I!ti) and connect all the bonding pads of the same signal on adjacent chips. .
以上のように本発明は、同じ入力信号について二個一対
のポンディングパッドをチップの対向する両側辺のほぼ
向き合った位置にそれぞれ配置することにより、チップ
を載設する基板上のポンディングパッド及びその接続配
ａｔ不要とし、その分だけさらに高密度の実装を行なう
ことができる。As described above, in the present invention, by arranging a pair of bonding pads for the same input signal at substantially opposite positions on opposite sides of the chip, the bonding pads on the substrate on which the chip is mounted and This eliminates the need for connection and layout, allowing for higher-density packaging.
第１図はチップをセラミック基板に実装した従来例の斜
視図、ｉａ２図は本発明の一実施例におけるボッティン
グパッドの配置図、第３図は不発明の集積回路チップ＜
−ｔｙｉツク基板上に実装し九斜視図ｔホす。
１・・・セラミック基板 ２・・・チップ４．４′
・・・ポンディングパッド
出願人 日不電気株式安社FIG. 1 is a perspective view of a conventional example in which a chip is mounted on a ceramic substrate, FIG.
- This is a perspective view of the device mounted on the board. 1... Ceramic substrate 2... Chip 4.4'
...Pounding pad applicant Nichifu Electric Co., Ltd.
Claims (1)
、ＩＩＩ記複数の端子としてそれぞれ二個一対のポンデ
ィングパッドを設け、これら二個一対のポンディングパ
ッドをチップ上面の対向する両側辺のほぼ向き合う位置
にそれぞれ一個づつ配置したこと全特徴とする集積回路
チップ。An integrated circuit chip equipped with a plurality of input signal terminals is provided with two and one pair of bonding pads as each of the plurality of terminals described in III above, and these two and one pair of bonding pads are connected to each other on opposite sides of the upper surface of the chip. An integrated circuit chip characterized by the fact that each chip is placed almost facing each other.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57067973A JPS58184735A (en) | 1982-04-22 | 1982-04-22 | Integrated circuit chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57067973A JPS58184735A (en) | 1982-04-22 | 1982-04-22 | Integrated circuit chip |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS58184735A true JPS58184735A (en) | 1983-10-28 |
Family
ID=13360435
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP57067973A Pending JPS58184735A (en) | 1982-04-22 | 1982-04-22 | Integrated circuit chip |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58184735A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61186252U (en) * | 1985-05-09 | 1986-11-20 | ||
| US8193626B2 (en) | 2007-06-20 | 2012-06-05 | Samsung Electronics Co., Ltd. | Semiconductor package including multiple chips and separate groups of leads |
| US9502345B2 (en) | 2008-05-21 | 2016-11-22 | Samsung Electronics Co., Ltd. | Ball-grid-array package, electronic system and method of manufacture |
-
1982
- 1982-04-22 JP JP57067973A patent/JPS58184735A/en active Pending
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61186252U (en) * | 1985-05-09 | 1986-11-20 | ||
| JPH054284Y2 (en) * | 1985-05-09 | 1993-02-02 | ||
| US8193626B2 (en) | 2007-06-20 | 2012-06-05 | Samsung Electronics Co., Ltd. | Semiconductor package including multiple chips and separate groups of leads |
| US9455217B2 (en) | 2008-05-21 | 2016-09-27 | Samsung Electronics Co., Ltd. | Semiconductor package including multiple chips and separate groups of leads |
| US9502345B2 (en) | 2008-05-21 | 2016-11-22 | Samsung Electronics Co., Ltd. | Ball-grid-array package, electronic system and method of manufacture |
| US8723333B2 (en) | 2009-03-17 | 2014-05-13 | Samsung Electronics Co., Ltd. | Semiconductor package including multiple chips and separate groups of leads |
| US8901750B2 (en) | 2009-03-17 | 2014-12-02 | Samsung Electronics Co., Ltd. | Semiconductor package including multiple chips and separate groups of leads |
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