JPS58184626A - Bus clock synchronization system - Google Patents

Abstract

PURPOSE:To increase a transfer speed, by generating signals which have a frequency as high as and are in phase with a bus timing and a basic clock signal generated in a CPU in an interface. CONSTITUTION:The basic clock signal X and bus timing signal V which have the frequency as high as and are in phase with the basic clock signal P and bus timing signal Q generated in the CPU300 are generated in the IF400. Bus data U transferred to the IF400 with delay of time TA as well as the bus timing signal is inputted to an input register at timing t1 where the AND of the signal V and X results in a failure. Then, the IF400 outputs transfer data U to a data line 202 through an output register 402 and a gate 403. The bus data U arrives at the CPU300 as bus data R with delay of signal propagation time TA.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a through-pass clock and resynchronization system suitable for a system equipped with an interface for transmitting and receiving data based on a path timing signal generated by a central processing unit.

[Technical background of the invention and electric point between them]

Generally, this type of system includes a central processing unit C (hereinafter referred to as cPU) 10, and an input/output channel interface (hereinafter referred to as IF) as shown in FIG.
11 to 14, etc. are connected to a path 15. In such a system, when performing high-speed data transfer via path 16, each! The method for distributing black and white as a standard for F11-14 etc. is 1゜Wow, no. 3 degrees and 1,2 degrees.

(Inside the chassis) Mother? As shown in the schematic diagram of the board, each IFM 7 ~14 were supplied with clocks independently to synchronize the timing.

However, with this method (1) Cable wiring tF field miscellaneous.

(2) Since the black and white signals are supplied to each IF separately, driver circuits for black and white feed are required for the number of IPs, which increases costs and makes it difficult to miniaturize the device.

(3) If the path needs to be extended to another chassis or enclosure, the cable wiring becomes more complex.

For this reason, in the conventional system, a timing signal is commonly supplied from the CPU JO to each IF77 to 14 via an unillustrated clock line of path J5. However, a method was adopted in which each of the IFs 11 to J4 outputs data to the path 16 using this path timing No. 411. Figure 3 shows an example of IFI when such a method is applied.
10 indicates the CPU J via the clock line (not shown) of path 15 (see Figure 1).
f-) to which the path timing signal transferred from O (see 1st column 1) is input.

Reference numeral 102 indicates an output register that reads and updates output data in accordance with the output signal of f-to-101, and 103 indicates an output register 102.
This is a dart that outputs the contents of to the path 16.

The operation of the IFI 3 (IFJJ, same for 12° and 14°) configured as shown in FIG. 3 in the system of FIG. 1 will be briefly explained with reference to the timing chart of FIG. 4. In addition, prior to this explanation, CPU 10
The basic clock signal generated within the CPU is
The path timing signal generated in JO and sent from the CPU JO to the clock line (not shown) of path 15 is defined as B. Also, the CPU in path J5
Add the path data near the JO connection position as C, and add the path timing signal near the IF13 connection position that goes to path 75 (internal clock line) as D1. Add the path data near the IF13 connection position on path 16 as E. * CPUJ
As shown in Fig. WJ4, the path timing signal B synchronized with the basic tarlock signal A is generated and sent to the clock line of the path J5. In this state, CPU1
In order for 0 to transfer data tl to 1113, path data C is transferred onto path 15 in synchronization with path timing No. 48B.
(N, see Figure 4).

In this history of path data C1, the path timing signal B passes through step 6, and as shown in FIG. The signals are then propagated to rFJJ as path data E and path timing signal, respectively. Also, the bus timing signal Dtj: is delayed by the gate 101 in IFJJ.

Next, IFI J deposits the pass data E based on the pass timing signal D (actually the output signal of r-) 101), and in the next pass cycle, the CPU J O
Assume that r-Y is transferred to . That is, IFJ J
outputs the path data E synchronized with the path timing signal D (actually the output signal of the #'i gate 101) as shown in FIG. ' - is sent onto path 15 via port 103. This Nox data EIIIi, C
As in the case of data transfer from PU 70 to rFl 3, there is a delay for the above-mentioned time, and the data is transferred to the CPU as path data C.
70 is input.

In this way, in the above-mentioned method, (1) the data transfer speed depends on the round-trip transmission length of the path (16) and the delay time of circuit elements such as darts (101); It is difficult to express the change.

(2) If noise is added to the path timing signal, data transmission and reception operations become impossible. For this reason, among the transmission lines that make up the paths on the motherboard, for example, only the black and Klein patterns for the pasta 4-turn signal are placed away from the other transmission lines and 9 turns to prevent noise. Must be prevented from riding.

There were drawbacks such as.

[Purpose of the invention]

The present invention has been made in view of the above circumstances, and its purpose is to
An object of the present invention is to provide a path clock synchronization method that is simple to assemble and can increase the data transfer rate via a path.

[Summary of the invention]

The present invention has a configuration in which a CPU (central processing unit) and an IP (interface) are connected to a path including clock lines, and a basic clock generator that generates a type 1 basic clock signal to the CPU; a first frequency divider that divides the frequency of the 18th basic signal by 1/N and outputs the 1mth bus timing signal; and means for guiding the first rare path timing signal to the clock line of the path. It is set up.

Furthermore, in the present invention, the above-mentioned interface 7A JK, □2,3゜2
゜゜゜゜゜゜゜゜゜゜power signal, and a phase gate and loop circuit are designed to control the phase ratio IIR signal generated in the i path so that it matches the frequency and phase of the input signal. In this phase opening and loop circuit, instead of directly using the output signal of the variable frequency oscillator as the phase comparison signal, the output signal of the Shimameku variable chest frequency oscillator is divided by 1/N by a second frequency divider. , this frequency-divided output is delayed by a time TI by a delay means, or further delayed by a time T, and the delayed output is used as the phase comparison signal.In the present invention, Considering each signal delay time due to the first and second frequency division numbers and the signal propagation time between the CPU and IF through the above path, if 〒1 is set appropriately for the first layer, then from K, the above flexible frequency The output signal of the oscillator can be used as a second type basic clock signal whose frequency and phase match those of the first type basic clock signal, and can be used as the branch output or "6-fold frequency division output" of the second divider. The signal delayed by one time period can be used as a type 2 bus tie establishment signal whose frequency and phase match those of the 18th pass timing signal.

[Embodiments of the invention]

Hereinafter, one embodiment of the present invention will be described with reference to the drawings. In Figure 5, 200 is a pass, and clock line 2
01 and data line 202. Reference numeral 300 has a CPU''C connected to the path xooK, and includes a basic clock generation section (hereinafter referred to as CLK generation section) 301 and a frequency divider (first frequency division I!!) JOJ.
The CLK generating section 301 generates a basic black signal P (first f11
The frequency divider 302 reduces the basic clock signal Pq)j[i1 wave number to 1/N (1/N).
It has a function of outputting a path typing signal Q by This bus timing signal QFi signal line 3
It is sent out to clock line 201 via 0B.

400 is an IF (ink 7 ace) connected to the path 200, and includes a phase-locked loop circuit (hereinafter referred to as PLL U circuit) 401, an output register 402, and a gate 403.

In the PLL excitation path 401, 404 is Clos, Klein 2
Path timing signal S input from 01 to IF I00
This is a phase comparator that takes the input signal as an input signal and compares the phase difference between this input signal and the phase comparison signal DA.The above path timing signal S is input from the CPU J 00 to the clock line 20.
The path timing signal Q sent out on the clock line 201 is a signal that propagates to the clock line 11400 over time T. That is, past tying number QFi
The diagram shows the hash timing signal near the C'PUSOO connection position on the clock line 201fC, and the hash timing signal S is also clock line 201.
CPU near the 00 connection position J 00 , I
The signal propagation time (propagation delay time) between the F 400 and 405d phase comparator 404 is integrated. A variable frequency oscillator that outputs the signal X, for example a voltage controlled oscillator (hereinafter referred to as VC)
In this embodiment, VCo 4 # #
The signal X output from the basic clock signal X (2nd'!
It is used in IF4IJO as a basic tarok signal). 407 converts the basic clock signal X to 1
A frequency divider that divides the frequency by /N, a delay means that delays the output signal of the 40aFi frequency divider 407 by a time Tl, for example a #i delay line (hereinafter referred to as DL).
The delay time T1 of g is the circuit delay time T0- of the frequency divider 302.
The circuit delay time T of 118 and 407 corresponds to 2. In this embodiment, it is assumed that TIf > Ta2. In this embodiment, the output signal of DL4oJ is determined by the has timing signal V (
It is designed to be used in Ir4O0 as a second path ion signal. 409 delays the bus tying signal V by a time T! delay means, for example DL (delay am
) - □ In this example, DL 409 j! The fly waiting time T1 matches the time TA (signal propagation time between the CPUs 300 and 11400).

The output signal from DL40 is supplied to phase comparator 404 as a phase comparison signal.

Next, the operation of one embodiment of the present invention will be explained with reference to the timing chart of FIG. When the CPU 300 is in operation, the CLK generator 301 constantly generates and outputs the basic clock signal P (see figure JI6).
as#'i This basic clock signal P is frequency-divided by IA (in this example N-2), and a path timing signal Q synchronized with the basic clock signal P is output. This lotus timing signal Q
is constantly sent to clock line 201 of path 200 via signal line 303. It should be noted that the hash timing signal Q is delayed from the basic taro signal P by the circuit delay time T11 of the frequency divider sag, as shown in the diagram ts6. In this case, the delay caused by the signal line 303 can be almost ignored.

The pass timing signal Q being sent to the clock line 201 passes through the clock line 201 to the CPU 36 with a delay of signal propagation time TAfeff between Ir4O1@, and is delayed as shown in FIG. It is input as a timing signal S to Ir2O3. The PLL circuit 401 operates so that the frequency and phase of the phase comparison signal 10, which is the output signal of the DL 409, match that of the path timing signal 8, which is an input signal inputted from the clock line 201. Turtle 6
The figure shows a signal s in a so-called system lock state in which the frequency and phase of the phase comparison signal da match those of the hash timing signal 8 due to the operation of the PLL circuit 401.
As is clear from the configuration of FIG. 5, in which s' is shown, the input signal of the DL409 that outputs the phase comparison signal da, that is, the lotus timing signal V, is equal to the delay time of the phase comparison signal l plus the delay time of the DL401. In other words, it advances by the time TA. As mentioned above, the lotus timing signal S is delayed by the lotus timing signal Q by a time T (see Fig. 6). Therefore, when the system is in the let state as mentioned above, the above The frequency and phase of the pass timing signal V match those of the pass timing signal MQ (refer to the stripe diagram 6). At this time, the output signal of the frequency divider 40'l is "III" 12 from the pass timing signal V. It's making great progress.

The output signal of the VCO 405, which is the input signal of the frequency divider 401, ie, the basic clock signal X, is ahead of the output signal of the frequency divider 401 by 2.

In other words, the basic signal P and signal X are the basic clock signals inside the CPU 300, as shown in FIG.

The frequency and phase match those of the signal P. As described above, according to the present embodiment, the basic clock signal X and the path timing signal V, which have the same frequency and phase as the basic clock signal P and path timing signal Q generated within the CPU 300, are provided. It can occur in Ir4O0. As a result, even if noise is added to the /4 timing signal Q sent from CPU J 00, there is no risk of it having any negative effect on the O data transmission/reception operation using Ir2O3. In the end, it is no longer necessary to arrange only Taro and Klein JOJ among the transmission lines and mother turns forming the bus zoot*, separating them from other transmission line patterns. Therefore, it is possible to improve the mounting efficiency of the printed wiring board in one mother board.

@CPU so assumes that CPU s o o transfers data to 11400 in this state.

When the CPU 5oo transfers data via the path 200 (data line; to2), the CPU 5oo sends data to the data line 2oz in synchronization with the path timing signal Q. Therefore, in this case, the path data on the data line 202 near the CPU J 00 is as shown in FIG. 6. In addition, in the figure, cpυ300 → IF40 (JFi
This indicates that the data is transferred from C1'U300 to 11P400. The above path data R passes through the data line XOX, and similarly to the path timing signal Q, the time TA! ! and propagated to Ir2O3. This ml, 11
The path data υ (shape II of data line 2o2) on data line 201 of 400 locations is as shown in FIG. For example, the signal V is input to the path data UFilF400.

Timing when the AND condition of X is not satisfied (time 1.)
is taken into an input register (not shown).

Next, in the next cycle of the data transfer pass cycle from CPU 3 o o to ryr4ooK, Ir
Suppose that 2O3 transfers data to CPU j 06. At this time, in synchronization with the path timing signal V, which is the output signal of the Ir4O0FiDL 408, the transfer data is output to the register 401, ? '-) 14 via 403
J j 00 Of-Send on the line soy. As a result, the state of the data line 202 near the IF 400, ie, the path data U, changes as shown in FIG.

Note that rF460-+CPU300 in the figure indicates data transferred from Ir2O3 to CPU j 00. The above path data U passes through the data line 202 and is transferred to CPo 300 after a signal propagation time T
reach. As a result, the state of the data line SEX near the CPU 306, that is, the path data R, becomes the state shown in FIG.

As is clear from the above description, according to this embodiment, cP
A path timing signal V (and a basic black and white signal
) can be generated inside the IF 400, and data transfer from Ir2O3 is performed in synchronization with this path timing signal V. Therefore, the delay time for data transfer from Ir2O3 to the CPU 300 is
The delay time of the one-way transmission path length between F 400 and CPU J 00 is 1/2 compared to the conventional method in which data is transferred using the path timing signal directly transferred from the CPU.

In addition, in the above embodiment, the circuit delay time T,, l T,2 of the frequency divider 302. This method can be easily applied in the case of 0, for example, T11 ``''''12, and the DL40J is not required. At this time, K is the frequency divider 40
The output signal of No. 1 is used as an input signal of the DL 409 and as a path timing signal V. t, T11 <
'rlz, the delay time T of the DL4011 is T-(Ti
2 Ti1 ) or T+("11"12)
Furthermore, as can be easily inferred from the above explanation, if n is an integer greater than or equal to 0, then the delay time T of the DL40g may be n-T ten (T11-te, 2).

(9) If m is an integer greater than or equal to 0, the delay time T2 of the DL 409 may be m-T+TA. As is clear, the above embodiment is a case where n=0 and me=Q. Also,
In the embodiment described above, the number of IFs connected to the node 200 is one, but the same implementation is possible even in the case of a plurality of IFs. In this case, it is necessary to select the DL4011 in each IF taking into consideration that T differs depending on the connection position of each IF with respect to the path 200. According to the path clock and resynchronization method, there is no need for a cable for compensating the propagation delay time of the path, there is no need to provide a dry circuit for supplying Mac clocks for the number of IP units, and the configuration is simple. Furthermore, although the configuration is simple, the r-to-data transfer speed via the path can be further increased.

[Brief explanation of drawings]

Figure 1 is a system configuration diagram showing a conventional example, Figure 2 is a schematic diagram of a conventional motherboard, Figure 3 is a diagram showing the main parts of a conventional interface (IF), and Figure 4 shows the operation of the conventional example. FIG. 5 is a main part block diagram showing an embodiment of the present invention, and FIG. 6 is a timing chart for explaining the operation of the above embodiment. 10.300...Central processing unit (CPU), 11~
14,400...Ink face (IF), IB, 2
00...Path, 102.402...Output register,
201...black, ri2in, 202...det2

Claims (3)

[Claims] (1) It is equipped with a path including a clock line, a central processing unit and an interface that are respectively connected to this path and perform data transmission and reception via this path, and the central processing unit is connected to the A basic clock generating section generates a signal, and the frequency of the 181st basic tarock signal generated by this basic clock generating section is divided by 1/N to output a type 1 bus timing signal #! 1 frequency divider,
Means for guiding the first fti1 path timing signal outputted from the first frequency divider to the clock line of the path is provided, and the interface is provided with signals on the clock and cline of the path as input signals, and the phase II so that the comparison signal matches the frequency and phase of the armpit input signal.
A phase-locked loop circuit that divides the output signal of the variable frequency oscillator by 1/N, and a second 8th divider that divides the output signal of the variable frequency oscillator by 1/N. I! A phase lock loop circuit is provided for outputting the phase comparison signal by delaying the output signal of Ji as is (7) or by a time T1, and then by a time T, and outputting the phase comparison signal. The signal is the #g2 type basic clock signal used by the above interface, and the output signal of the second frequency divider or the signal obtained by delaying the output signal of the @2 frequency divider by time TI is used by the above interface. A path clock synchronization method characterized by using a path timing system. (2) The period of the first glaze pass timing signal is T,
If n is an integer greater than or equal to 0, the above time TI is
2. The path clock synchronization method according to claim 1, wherein the sum is the delay time of the first frequency divider minus the delay time of the second frequency divider. (3) If m is an integer greater than or equal to 0, the above time Tm is m-
The path clock resynchronization method described in the button of the patent claim, box 2fJR, characterized in that it is the sum of T and "the signal propagation time between the central processing unit and the interface by the above-mentioned!".