JPS58181355A - Frequency discriminating system - Google Patents

Abstract

PURPOSE:To demodulate a signal applied with FSK modulation without being affected with waveform deformation of a signal, by delaying the 1st and the 2nd pulse trains by an integer multiple of the period of the trains, and detecting the amount of coincidence with the 1st and the 2nd pulse trains. CONSTITUTION:An FSK signal is converted into the 1st and the 2nd pulse trains arranged serially timewise in the form of binary signal at a forming circuit 315. The signal is delayed for an integer multiple of the period of the 1st and the 2nd pulse trains at a shift register 317 and outputted to taps 2, 3. The output of a tap 1 and the taps 2, 3 being the 1st and the 2nd signal train output is inputted to exclusive OR circuits 318, 319 and this output controls an up-down counter 320. Then, the amount of coincidence between the 1st, the 2nd signal trains and the delayed output is detected, allowing to discriminate the presence of the 1st and the 2nd frequency components.

Description

[Detailed description of the invention] Honka F! A relates to a frequency discrimination method for demodulating the original digital signal from a signal that has been modified and transmitted using the frequency diad keying (78K) method, which is one of the modulation methods for digital signals. This is to prevent the effects of waveform distortion due to fading or the like when transmitting the signal.

At present, a wide range of systems have been developed in which, for example, a digital code is sent in a medium wave broadcast signal and a receiver is controlled using the digital code. One of these systems, the emergency warning broadcast system, sends a special signal before the broadcast begins in the event of an emergency to start the receiver's operation, and then VCs to ensure that the emergency warning broadcast can be heard. . A digital code pattern is used as the control signal for this 7-stem signal, but when transmitting the 7-stem signal, FSK modulation is performed using the signal g at the audio frequency range, and the shape of the modulated signal is to be transmitted as an audio signal. In the case of a co-valued signal, λ audio band frequencies are used corresponding to each of the levels @111 and 01 of the digital signal.

One such system, the 1920 Showa SR Radio Technology Council Report Volume D and the Radio Technology Council Deliberation Materials [Temporary Standards for Emergency Warning Signaling System], or the ``Specific Program Broadcasting Transmission and Reception System'' proposed by the applicant (Unexamined Japanese Patent Publication No. 54-965
4'j), the basic configuration of the signal system will be explained with reference to FIG.

Here, the digital signal is configured in a binary NRZ format with a unit of 16 pints, and the signal frequency is 1, and the degree of deviation frequency f13 is 13 for the level @, @ of the signal.
1 /Qko II Hz f @ guess, level “o” <
For this purpose, a reference frequency f @ = 6'lOHz f is assigned, and the code is transmitted at a code transmission rate of 6 duvints per second.

The present invention is designed to address a receiving method that demodulates the original digital code pattern from a signal modulated to F8.

Although it is not limited to the value of the code transmission rate, in order to make the explanation more concrete, the above numerical values will be tentatively used in the following description.

As shown in Fig. 2, a typical method for reproducing a signal transformed into F8 is to apply a signal power of 10/ to KF8 and apply bandpass filters lQ and /( 113 and those filters 10
The envelope detection circuit 103 and ios, which are the outputs of 2 and 103, perform envelope detection, respectively, and supply it to the detection can comparator 106, which compares which frequency is larger, and generates a digital signal as a 70-meter result. Output t07
There is a receiving method that can be used.

This reception method works fine if one frequency component of the signal is received according to the standard, but if the signal is subjected to waveform distortion during transmission, the operation becomes uncertain.

An example of this type of situation is short-distance broadcasting in the case of medium wave radio broadcasting. This is due to interference between surface waves and ionospheric reflected waves, resulting in frequency selectivity 7eding, which can cause severe waveform distortion in areas where the intensity of the reflected waves is close to #II degree of the surface waves. be. This distortion changes from moment to moment.

Most of the signal is recovered within a few seconds, but during this time the signal wave modulated to F8 by the code undergoes waveform distortion and generates harmonic components, so it is not received correctly.

The operation of the emergency warning broadcast system may be delayed.

Therefore, in order to further increase the reliability of the system, it is necessary to develop a receiving system that eliminates this delay and operates quickly.

If the signal waveform is distorted, the operation of the receiving circuit shown in Fig. 2 may become uncertain due to the following reasons. (
An output is output to the filter lOJ of 102 (IHz), and an output is output to the filter lOJ of the reference frequency fm (1, uOHz).The period of the "0" signal is the reference frequency f: (6
The output is output to the filter 1041 of 'lOHz), and the filter 102 of the number 11 (10-reference Hz)
There is no output. However, if the waveform is distorted and, for example, the -th harmonic appears at 6th OHz, the period of the level @O° signal will include components of the reference frequency of 641 OHZ and the fourth harmonic of the reference frequency of 1210 Hz. Become. The stiffness 1-10 Hz component is the reference frequency 12-=44'(
The deviation frequency of the 7Hz filter 104I is fg =
The 10 filters in the 102'l kit produce more output. This amount is 61IOHzIiii, 44IO per minute
If the output is greater than the output generated by the 10Hz filter, it will be determined that a signal with a level of If more output is output to IO-, it becomes impossible to detect the period code of seven.

One method for dealing with such a situation is path (b) shown in FIG. Here, we consider up to the second harmonic among the harmonics that are applied with % distortion of 4, and set the signal to F8 by 20/
Y f t = 10 pieces II Hz processing f1 - λ0
111rHz bandpass filters 〇2 and 20
1! , parallel fl = 61IOHz and cofl
-1210 Hz band pass filters 12 and 12 are supplied to each envelope detection circuit 203 and 1210 Hz band pass filters 12 and 13 to each envelope detection circuit 203 and 1210 Hz. The two synthesized outputs obtained by synthesizing each of

The comparator 206WCL') compares the two synthesis chips to obtain a digital signal output 207.

When we conducted a reception experiment using this circuit, we found that the reception operation was reliable even with distorted signal waveforms. However, in this circuit, 117 bandpass filters are used: oJ, sot, co0# and co10
If the value of the envelope detection edge for each filter output is not adjusted correctly, the operation will become uncertain, so there will be some problems in circuit design and adjustments during manufacturing. . Moreover, when such a circuit is integrated, external attachment is considered to increase the number of parts, which is not a good idea.

SUMMARY OF THE INVENTION It is therefore an object of the present invention to eliminate the above-mentioned drawbacks.

FS without being affected by signal waveform distortion
The object of the present invention is to provide a frequency discrimination method 1kf that can generate a Kf II times signal aIM.

In order to achieve such an object, the present invention has been devised to provide at least a plurality of first and second frequency components, the first and first frequency components being arranged in series in time. In a frequency discrimination method that receives a signal wave having a frequency component of means for forming a second pulse train into a second pulse train; and a pulse signal train comprising the first pulse train and the first pulse train; delay means for extracting first and first delayed pulse signals each delaying the pulse signal train by a delay time that is an integral multiple of /Y of the period of the pulse train;
Coincidence detecting means for comparing the first delayed pulse signal from the delaying means with the pulse series 'fAJ' and detecting a coincidence.

The present invention is characterized in that it includes a discriminating means for discriminating the presence of the first and second frequency components as described in 11.1 above.

The present invention will be described in detail below with reference to the drawings.

The present invention performs multiple IM of signals on F8 with the following points in mind. Now, the signal frequency f! Suppose that a sine wave of is transmitted. If this signal 'l 'I'l (=//f+) is delayed, it completely overlaps with the original signal as shown in Figure (A) VC, but only by the time Ta = (//fz). If they are delayed, they will not overlap.On the other hand, when a sine wave of signal frequency fi is transmitted, as shown in Figure (B),
If they are delayed by the time T, C=//f, ), they will not overlap, but if they are delayed by the time Tl(-//fs), they will overlap completely.

In the present invention, this property is utilized to discriminate signal frequencies. Here, even if the waveform of each signal frequency is distorted and contains harmonics, both the analog signal waveform processing and the digitized output are processed according to step 5 shown in Fig. 5 (A) and CB). Tl(=//fl) or Tm(-//fx
) and compare it with the original signal, it matches the delayed signal of the original signal and the delayed harmonic signal according to each delay time. In other words, even if harmonics are generated due to waveform distortion, if each signal consists of a waveform with a period of T or T, it can be recovered by utilizing its synchronicity. However, if the distortion situation changes over time, the VC level will not completely match, but the change will be T+ (fI-
0.91 mm at 10 Hz), or ks
Tz (/寞-6#When Off1l/, 56m5)
If the time is sufficiently slow compared to the time shown in FIG. For example, this condition is fully satisfied with respect to distortion -'zK caused by short-range fading of store radio broadcasts, which are currently mainly considered to be arriving at the same time. Note that if one of the signal frequencies is an integer multiple of the other, VC cannot be recovered using this method, so the reference frequency and shift frequency are determined so that one is not an integer multiple of the other.

An example of an FSK demodulation circuit using the frequency discrimination method of the present invention is shown in FIG. Here, analog FSK Ibi No. 3 input
01 k Supplied to filter J/II. This filter 3
The standard frequency is 12 = 6'10 Hz, and the standard frequency is 12 = 6'10 Hz.
and the frequency component including sIm modifier fx=10Hz is extracted. This filtering process is repeated in F8.#1 [i] For example, when the signal is the audio of a broadcast program and is sent at °C, the K, 87 N ratio is sufficient to ensure the VC. K is this filter 314! does not require rigorous design. The sine wave output of the filter 31' in the voice band is supplied to the Y shaping circuit 31j.

Here, the signal 31B is converted into F8 in the form of a digital signal with a λ value as shown in FIG. 7 (LA) and [ν].

Specifically, the shaping circuit 3/6 can be configured with a high gain amplifier, a Schmint trigger circuit, or the like.

This digital F8 has a signal J16 in the form of 6 seconds Hz.
The pattern of the 10 Koda Hz component is compared in degrees Celsius as follows to see if it matches the desired periodic pattern.

A signal J/4 Y: y y tresistor 317 K is sent to the digitized F8. This shift register J/
By appropriately excursion of the number of stages of the tap output of 7 and the clock signal Jλλ, the cabinet of the tap λ and the tap l becomes T1 (=i/h−
The delay between the tamp J and the tamp I is set to be T mushroom (= // fm -, // 4 seconds). For example, the relationship between tamp λ and tamp l'
l Nt −, 5 stages, relationship tN between tap J and tap l,
= 1 stage, clock g! I No. 3 λ 1 clock frequency V S / KO Hz L 10 λ reference Hz and 64! Eel Kokobe 1j with OHz! i, ), the above relationship is satisfied. Outputs 323 and 3λ of Tampl and Tampco
11 If the exclusive M summation of these two outputs is obtained by supplying it to the other-earth phase circuit 3ty, when both outputs match, 01
When there is no match, l is obtained.

FIGS. 7(B) and (G) show the Tl delay signal 32 from TAMPCO, and 71CD) and (I) show the Tl delay signal 32 from TAMPCO.
The T2 delayed signal 3λSv from is shown. When FSK frequency frequency-transfer frequency/l = 1o-GHz, outputs 3λ3 and 3 of amps 1 and 3 are used as exclusive-rational sum circuit 3/1
As a result of comparing the output 3 and 4' ks, the pulses are delayed by the time Tl from the pulse of the output 3 and 3, so the waveforms of both outputs completely match, and as shown in Figure 7(C), the VCC exclusive logic The sum circuit 3ir output 3 continuously becomes "0". Outputs 323 and 321 of tamp l and tamp 3
1: As a result of comparison with exclusive OR circuit J/9, output 32
5 ks Output 3 J pulse time Tl 2t/g
Since the pulses are delayed by 2=//6 da by 0 seconds, the output J core for each 1ft31 exclusive decoupling circuit will be inconsistent for only 10% of the 5K/period as shown in Figure 7 (CB).
l” output is obtained.

On the other hand, when the FSK frequency is the reference frequency f/Q Hz, as shown in FIG. 7 (I() and (J)K).

The output J core of the exclusive 11M sum circuit 311 is inconsistent for a period of 7% of the period of X, and an 11° output is obtained. 1o'' continuously.

The respective outputs 3 and 3-7 of the exclusive OR circuits 3/I and 319 and the clock signal 3 are supplied to the 3 amplifier down counters. This amplifier down counter 3
KO Ok This is an example of a circuit.This counter 3-0 is a binary counter, and when taps lN2 match (10 pieces II H
z detection), the output Jλ4 becomes @0'', the count value increases, and when the taps lN3 match (detection of 64tOH), the output J core becomes 1o'' and the count value decreases. There is.

Counter control circuit 3λ/ is amplifier down counter 320
#II is configured to receive the output 326 and the carry output C from the 3 cores and the counter 320 and stop counting in the case of 5th order. Output 321 Supplies 3 f counters OK.

(1) Exclusive OR circuit J/If and output 3 of 319
For example, m 7 if the cores and cores are the same.
elJ (E) M Yohi (H) TiCM Kel “o”
Rehel o) period].

(2) When the contents of the counter 320 are already at the high value, an input is input to further increase the count value.

(5) When the contents of the counter 320 are at the minimum value 1c, an input is made to further lower the counted value.

In the above configuration, if we assume that the shift frequency component, i.e., the 10-Hz component, is received during the period C, then the exclusive Counter 320 ks count and amplify.

During this period, the exclusive picture border sum output 327 becomes 10'' for a 1% period (LE in Figure 7 @0'' level period) VC is output 3
Both Koro and 3 cores will be @0@ level.

Stops the count amplifier, but outputs 3 cores Q @,
When it becomes T-, the output 3λ6 is 10" (continue counting during the remaining to% period, and 10 cols.
As long as the pulse train continues, the count-up II continues. However, only when the output 3 core becomes @O''', the 7 count amplifier is temporarily stopped and the count value at that time is maintained.In this way, when the count value reaches a certain value, further counts are stopped. Amplification is not done.

In other words, the M8B output terminal of the counter 320 outputs a signal "l". This signal is the pulse waveform of the above-mentioned control signal sent from the transmitting side.
The level will be restored.

Next, when the period when the reference frequency signal 5f%, that is, 6 daOHz is being received, the counter 320 counts down during the period when the output 3 core is 10". However, the output 3 core is @O". The period of coS% (Figure 7 (H)
0) During the "0" level, both the output 3 and J core will be @ 0", so the countdown will be temporarily suspended, but the countdown will be temporarily stopped during the 7S% period at 8:00 when the output 3 is 11". The e-countdown continues, and the e-countdown continues as long as the @O'' period continues on the output 3λ7.

However, once the count value reaches a certain value, the countdown is no longer performed. At this time, a signal of level 101 is output from the MOB output terminal. The stiffness signal is the pulse waveform of the above-mentioned control signal sent from the transmitting side.
``The level will be restored.

In the manner described above, the waveform of the pulse train of the control signal sent from the transmitter is restored.

With the above configuration, 1 For example, in the case of Ko-shin counter 320 or Moku-shin, M8BCI & upper focus) @! If it is output as the digital signal output 307, the deviation frequency V number f, (1
For the input of the reference frequency fz (6≠(7Hz)), the output is 10''. With the above step 5, the signal Y: demodulates at 1i'8. can.

The above is the basic configuration of the present invention, but 152FjA is added to each unit. First, the number of shift registers 3170 stages and clock frequency will be described.

I mentioned it before.

The cabinet of taps l and 3 is t stage, Cronk frequency is j/λO
If Hz is equal to Hz, the delay between the buttons L and K is t/ios.
*Seconds, the distance between tamps l and 3 is l/6 da. seconds. However, for example, if there are only 10 samples within the 4th period, the 6uOHz signal (on the other hand, the positions for matching or mismatching judgments will be quite sparse. Therefore, depending on the sampling phase) Considerable variation may occur in the match and mismatch count values.In order to improve this point and achieve stable operation, it is necessary to increase the sampling Y@Kj, that is, the Cronk wave number.

Now, if we make the sampling N times denser than in one example, the Cronk frequency will be lλkHzXN, 77) Register J1
INN is between 70 stages 1 etampe l and 2.

The darkness between taps l and 3 is 18 steps.

Next, regarding the number of stages of the A1 down counter JCO0, the response becomes faster. That is, when the input signal changes from one frequency to the other, the number of clocks required until M2R (top focus) of counter 30 is inverted is small, and the detection output changes immediately. Conversely, if the number of stages is large, the speed to follow changes will be slow. On the other hand, when noise is added to the input signal, if the number of stages of the counter 3λ0 is large, the effect will hardly appear on the output, but if the number of stages is small, the IC will be sensitive to changes in the count value due to noise that will not appear on the detection output. It becomes.

Therefore, when the 8/N ratio of the transmission path through which the signal is transmitted to F8 is low, the noise can be significantly reduced by increasing the number of counters (3200 stages).

Generally speaking, if the number of stages of register J/7 and the number of stages of counter 3 and 0 can be reduced, it will be simplified in terms of the number of circuit elements, but the high concentration of two circuits will increase. Nowadays, this simplification does not need to be too long.

By the way, integrating circuits [1alj! 6 (IC) and the stages av between Tano 7/, λ, and 3 of the general-purpose register 317 may not be freely selected. If an element with a large number of stages between each tap is used, it is necessary to increase the tarock frequency in order to obtain the desired value of the delay time Y at each tap. In this case, it is necessary to increase the number of stages of the three counters Q in order to avoid the influence of IC noise as described above. However, it was devised that a clock frequency reduction circuit was provided in the counter control [gJwIJλl, and its output was used to control the counting operation of the counter 3λO.

Equivalent operation can be performed with a counter with a small number of stages 1゜The operation of the counter control circuit 3 described earlier [In 8 clearly, under the conditions (2) and (5) for stopping counting, the counter 3 There are cases where the contents of KO become a very high value or a &1 minimum value, but these highest values or lowest values can usually be treated as values determined by the counter circuit used, but the signal changes from @l'' to @ When changing from °O" to @l
In cases where it is necessary to obtain a response error [%-precision vclhi] when changing to ``, the frequency discrimination method 1 of the present invention can be achieved by setting the highest count value and the lowest count value as necessary.
From VC.

The following effects can be achieved.

(1) Even if a signal is subjected to waveform distortion Y due to selective aging or the like, the signal can be detected without being affected by the distortion. As a result, the problem of slow operation that was observed in the emergency warning signal transmission experiment is resolved. In this case, the fact that the energy of the third harmonic component does not depend on IVC compared to the receiving method that takes into account the second harmonic component of VCC as shown in FIG.

(2) Frequency discrimination is performed entirely digitally, eliminating the need for 1111 circuit constants of analog circuits, and operation is extremely stable. Among the constants that determine the characteristics, the product is vague.

There is only the basic clock frequency l. This is the same crystal generator as the clock used for the detection (9) path of engineering emergency warning signals. It can be created by dividing the frequency from a frequency converter, and a stable long signal can be obtained.

In application fields such as kite emergency warning broadcasting, there is a large difference in reliability due to variations in receiver manufacturing.
However, according to the present invention, it is possible to make the performance γ the same as that of J6.

(3) Figure J Q) Digitalization of parts including capacitors and resistors such as bandpass filters and detection circuits for each signal frequency, which were necessary in the conventional example. It is suitable for large-scale integrated circuits.

[Brief explanation of the drawing]

Fig. 1 is an explanatory diagram of the structure and transmission format of the emergency warning signal, Figs. ) Signal waveform diagram for explaining the principle of demodulation at F8 in #4, Figure J LA) and (B) (Signal waveform diagram 6 showing analog and digital signal waveforms when the engineered waveform is distorted 7(A) to (J) are signal waveform diagrams of various parts of the circuit shown in FIG. 6. 10/...F8K @ number input, 102 .to
II ・-/(donos(filter), 1
03.10!・Envelope detection circuit,
to6...Kono Kureta. 107-Digital signal output. ko0/... Signal input to F8. Ko Oλ, λO Hiroshi, 201. Ko 10...Pantonoku Sufilta. 203, 201. Ko09. Koti... Envelope detection circuit, 212, Ko13-Synthesizing circuit, λ06... Connoctor, 207... Digital signal output, 30/... Signal input to analog F8, 37 Tar-- Filter , 31j... forming circuit, 314...
Signal to digital F8. 3/7.../Futo V Sosta. 311, 319... exclusive OR circuit, 320...
Amplifier down counter, 32/...Counter control circuit, 3 here...Taronk signal, J co3...Tamp 113λda...Tampco, 3λj...Tamp 3.3, 3 core...- Exclusive OR output, 3 pieces... Counting stop output. Figure 5 (A) (B) Figure 6-Figure 7

Claims (1)

[Claims] A first and a second frequency component;
In a frequency discrimination method, a signal wave having at least one frequency component arranged serially in time is received and the presence of each of the first and body frequency components is discriminated. means for forming first and second pulse trains arranged serially in time in the form of a value signal;
and a second pulse train is supplied with a ttr pulse signal train, an integer multiple of the period of the first pulse train including l and the ! ! The #1 # and #2 delayed pulse signals are respectively delayed from the pulse signal train by a delay time that is an integral multiple of the period of the pulse train of #1, and the #1 # and #2 delayed pulse signals are outputted from the delay means and the and a coincidence detecting means for comparing each of the second delayed pulse signals with the pulse signal train to detect a coincidence, and detecting the amount of coincidence (the existence of the first and first frequency components). 1. A frequency discrimination method characterized by comprising a discrimination means for discriminating frequencies.