JPS58171842A - Integrated circuit device - Google Patents

Abstract

PURPOSE:To reduce power consumption of an integrated circuit device by adequately selecting an operating voltage of function circuit block in accordance with an input clock frequency and by setting it to the optimum value. CONSTITUTION:An input clock frequency detection circuit 1 outputs digital data Q1-Qn of clock frequency from an input clock CLIN. A regulated power supply circuit 2 generates m-fixed voltages V1-Vm of a low voltage from an external power supply input VDD. A power supply selection circuit 3 outputs power supply selecting outputs S1-Sm from digital data Q1-Qn. A switch group 4 selects one voltage VDIN from the constant voltage group V1-Vm by means of the outputs S1-Sm and supplies this voltage VDIN to a functional block 5. With this structure, the circuit 1 detects the input clock frequency, operating speed of the functional block circuit and controls an operation voltage to the optimum value, thereby reducing power consumption.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a circuit device having an operating voltage conversion circuit that variably sets the operating voltage supplied to a functional circuit block in accordance with the operating speed of a system.

In recent years, systems using complementary MO8 integrated circuits have come into widespread use for the purpose of low power consumption. Generally, the operating speed of a complementary MO8 integrated circuit is proportional to the operating current, which in turn is proportional to the operating voltage. Therefore, in order to reduce power consumption, it is desirable to lower the operating voltage as much as possible within the range where the operating speed achieves the intended use.

Incidentally, in integrated circuits used for general purposes such as microcomputers, internal functional circuit blocks are designed to ensure high-speed operation that satisfies the specifications within the power supply voltage range specified in the specifications. For this reason, conventionally, even in the case of low-speed operation, internal functional circuit blocks have been operated at an operating voltage that allows high-speed operation, resulting in wasteful power consumption.

The present invention has been made in view of the above-mentioned drawbacks, and the present invention has been made in consideration of the above-mentioned drawbacks. It is an object of the present invention to provide an integrated circuit device that can appropriately select and set the optimum value.

Hereinafter, the configuration of the present invention will be explained using examples.

FIG. 1 is a basic block diagram of an integrated circuit device according to an embodiment of the present invention. This configuration includes an input clock frequency detection circuit section 1, a constant voltage power supply circuit section 2, a power supply selection circuit section 3, a switch group 4, and a functional circuit block 5. The input clock frequency detection circuit section 1 has an input clock CLII.
By I, digital information Q1 to Qn of clock frequency
Output.

The constant voltage power supply circuit section 2 generates m fixed voltages v1 to 'Irn that are lower voltages than the external power supply VDD. The power supply selection circuit section 3 receives digital information Q1 about clock frequencies.
Qn outputs power supply selection outputs 81 to am. The switch group 4 is connected to the constant voltage group v by the power source selection outputs 81 to Sm.
One voltage Vt+ns is selected from 1 to Vm and this voltage VDIN is supplied to the functional circuit block 6. In the same figure, s
', es% are other functional blocks corresponding to the functional block 6, and a/, 3/F, and 4', 4' are also corresponding power supply selection circuit units and switch groups.

The details of this configuration and function will be explained below by breaking it down into each block. For simplicity, the explanation will be based on a case where there is only one functional circuit block.

FIG. 2 shows the circuit configuration of the input clock frequency detection circuit section 10. This circuit consists of an OR series circuit that sandwiches an analog switch 6 between a capacitor C and a resistor R, a D-type flip-flop 7 that turns on and off the analog switch 6, a waveform shaping circuit 8 that forms gate pulses, and an input clock. Consists of an AND gate 9 that performs gating, a one-stage counter 1o that determines the frequency detection period, a three-stage counter 11 that counts the gated input clock, an n-stage switch 12 that holds the count result, and an inverter 13 that inverts the gate pulse. be done.

An external human clock OL l is connected to the flip type flip 70 knob 7 to which the power supply Van supplied from the outside is connected to the D input.
When yr is input, its Q output becomes H''.,7
This allows the OR
The analog switch 6 between the ORs of the series circuit is turned on.

Then, the initial value is set to the external power supply voltage VDD at both ends of the resistor H.
An exponentially decaying signal with an OR0 time constant is generated. This signal is shaped into a pulse wave by a waveform shaping circuit 8 that connects a plurality of inverters, and the input clock OL
Let x* be a gate pulse with a period T to be counted. FIG. 3(a) shows the output of the OR series circuit, and FIG. 3(b) shows the output of the waveform shaping circuit 8. The gate pulse width τ is determined by the external power supply voltage VDD, the capacitor C9 resistor R, and the input threshold voltage Vs+w of the inverter. The relational expression is shown below.

V+sw=VDD 6! p(-cFl)・T
VDn...τY=T' The gate pulse with pulse width T causes the input clock O
Gate Lxw with AND gate 9, 3-stage counter 11
to obtain counter outputs Q1 to Qn proportional to the input clock frequency. When the final stage counter output Qn becomes 'H', the concomitant output Qn is input to the AND gate 9 and clock input is inhibited. 12, it is stored in synchronization with the falling edge of the gate pulse.The above operation is performed by turning on the analog switch 6 between the respective ORs of the output signal Qe of the one-stage counter 1o (n>n) that operates with the input clock 0Lxx. , in addition to each reset input terminal of the D-type flip-flop 7 and the three-stage counter 11 to be turned off, the period To (however, To = tOX2',
to: input clock period).

FIG. 4 shows an example of the circuit configuration of the constant voltage power supply circuit section 20. m IC/XC/X type medium channel MOS inverters, the input terminal 14 of each MO8) transistor Tr is set to ground level, the first stage power supply is connected to the external input power supply VIID, and the second stage and subsequent stages The power supply of each stage is connected to the output of each previous stage. As a result, in the first stage vl, V1=VDI1, and in the second and subsequent stages, when the influence of the substrate bias effect is small, Vi#Vnn-isVy (L=1.2.-, rn
-1) Vte: Kln-channel MOS transistor T
A voltage of the threshold voltage of r is obtained. In this way, the functional circuit block 5.
Each power supply line 5' and 5' has V at the maximum operating frequency.
DD, and as the operating frequency becomes lower, the voltage value is sequentially lowered and supplied. The power supply selection circuit section 3 is composed of a combination of MOS/analog switches, and selects an input from among the analog switches that connect each output voltage from the constant voltage power supply circuit section 2 and each functional circuit block 5.5', 5'. The configuration is such that a logic gate selects one operating voltage based on the counter outputs Q1 to Qn of the clock frequency detection circuit, turns on the analog switch capable of supplying that operating voltage, and turns off all others.

FIG. 6 is a detailed circuit diagram showing one system of the present invention. The input clock frequency detection circuit section 1 converts the input clock gated by the AND gate 9 into a 7-stage counter 1.
1 counts up to 64 pieces, outputs Q1 to Q7, and stores them in the 7-stage latch circuit 12. In addition, a 10-stage counter 10
By the way, every time we count 210 input clocks,
Repeat this action. The constant voltage power supply circuit section 2 uses two K/type n-channel MOS inverters to supply VDD to the first stage power supply, VtID-Vy to the first stage output, and VDD-2Vt to the second stage output. Obtain each voltage. The power supply selection circuit section 3 and the switch group 4 include a 4-person cutter gate 16, a 2-person cutter gate 16, and 3 analog switches 81 and 82°S3.
The input clock count number is 0 to 7, the operating voltage is selected to vnn-2vy, and the input clock count is 0 to 7.
VT, select 64 te vDD. FIG. 6 is an operation timing chart of the circuit shown in FIG.
sQ5*Q6sQ'H Output S1, 8 of power supply selection circuit section 3
2. Ss and the functional circuit block 6 selected at that time
represents the operating voltage. Here, in order to replace the number of input clocks with the input clock frequency, the gate pulse width T is set to 20
If we take μ1llec, the optimal operating voltage of each functional circuit block is V3=VDD-2Vt below 4001H1.
.

V2 = VD1 at 400 KHz or more and less than 3.2 MHz
1-Vt.

3.2MHz or higher tev1 = vDD tonal.

As described above, the present invention detects the input clock frequency to know the operating speed of the functional block circuit, and adjusts the operating voltage of the functional circuit block to a low voltage during low-speed operation, for example, according to each operating speed. , each can be set to the optimum operating voltage, which has a great effect on reducing the power consumption of the integrated circuit device. 5. , - Furthermore, the above explanation i: Complementary! Regarding circuit example 4 suitable for MO5 integrated circuit, we conducted a circuit example 4 which is suitable for MO5 integrated circuit.
Of course, it is also applicable to any .

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an integrated circuit device according to the present invention, FIG. 2 is a diagram of an input clock detection circuit, and FIG. 3 is a diagram of an input clock detection circuit, showing the output of each part in the gate pulse forming process. (&) is a CR series circuit output waveform diagram, and the figure (b) is a waveform shaping inverter. 1... Input clock frequency detection circuit section, 2...
... Constant voltage power supply circuit section % 3 e 3' + 3"
...Power selection circuit section, 4.4', 4"...
...Switch group 6, 5/, 5//...
Functional circuit block, 6...analog switch,
7...D type flip-flop, 8...
Waveform shaping circuit %9...And gate, 10.1
1...Counter, 12...Latch, 1
3... Inverter, CL engineer... External manual clock, V1. V2...Vm...
Constant voltage power supply circuit output, Ql, Q2...Qn...
...Enter. 2□ff1i! i*Ifl[IM[]
, S 1 , S 2-'-11, -Sm 0. −・・
・Power supply selection circuit output. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
Figure 2 Figure 3 (αl (bJ Figure 4 @ Figure 5

Claims (2)

[Claims] (1) A frequency detection circuit that detects a clock frequency input from the outside, a constant voltage power supply circuit that generates two or more types of constant voltages, and an output of the constant voltage power supply circuit as appropriate according to the output of the frequency detection circuit. An integrated circuit device 0 characterized in that it has a power supply selection circuit that selects and supplies a predetermined voltage to a functional circuit. (2) The integrated circuit device according to claim 1, wherein the frequency detection circuit has a multi-stage counter, the counter counts an external clock, and sequentially obtains a counter output.