JPS5816764B2 - Memory circuit control device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a control device for a storage circuit, and is capable of writing and storing information signals for controlling the operation of a controlled device in the storage circuit, and reading out the stored information signals. The present invention relates to a memory circuit control device for controlling a channel, and particularly to a memory circuit control device suitable for storing a channel selection voltage supplied to an electronic tuning tuner used in an electronic channel selection device of a television receiver. It is.

Conventionally, a so-called electronic tuning tuner using a voltage variable reactance element as a tuning element is provided, and a tuning voltage set by a potentiometer provided corresponding to each channel is supplied to the variable reactance element of this tuner to tune a predetermined channel. In recent years, an electronic channel selection device using a potentiometer has been developed.

In other words, the channel selection voltage, which is an analog quantity, is converted into a digital quantity,
This is stored in a semiconductor memory circuit in advance, and when selecting a channel, this digital signal is read out, converted to an analog signal, and applied to an electronic tuner.

In order to digitally quantify the channel selection voltage, for example, the channel selection voltage may be treated as a pulse voltage whose duty changes, and thereby the channel selection voltage can be easily converted into a digital quantification.

That is, it is sufficient to create a pulse voltage that changes this tutee from the two communication signals, and convert this pulse voltage into a DC voltage through a low pulse filter or the like.

To create a pulse voltage with varying duty from two communication signals, for example, two binary counters with the same number of bits, a comparator that compares the output of each bit of each counter, and the initial state of one counter are detected. First, one counter is operated at high speed using a gate circuit and a latch circuit.

At this time, each bit of the other counter is set to a predetermined state, and the latch circuit is set by the pulse output from the gate circuit in the initial state of the high-speed counter, and when the output of each bit of the two counters matches, the comparison is made. The launch circuit is configured so that the pulse output from the device resets the launch circuit.

Thereby, a constant pulse voltage having a predetermined pulse width and a constant period can be obtained as the output of the latch circuit.

Therefore, by changing the output of each bit of the other counter, a pulse voltage with varying duty can be obtained.

When such an electronic channel selection device is applied to a television or receiver, for example, the output of the gate circuit that detects the final state of the high-speed counter can be used as is, or it can be divided and output to the other counter (low-speed counter). Add it as a clock pulse to

Thereby, the pulse width of the pulse voltage that is the output of the launch circuit is automatically changed, and when a predetermined channel is received, this is detected by the automatic tuning control circuit AFT, and the input of the clock pulse applied to the low-speed counter is prevent.

At this time, the output of each bit of the low-speed counter is stored in a predetermined address of the storage circuit, and after the storage is completed, the low-speed counter is operated again.The same operation is repeated thereafter, and each bit of the low-speed counter corresponding to each channel is output. is stored at a predetermined address in the memory circuit.

Therefore, for channel selection after storage is completed, it is sufficient to set the signal stored in the storage circuit in a low-speed counter.

To actually carry out the operations described above, a control device is required to control the memory circuit.

In other words, a control device is required to control the switching of addresses in the memory circuit, control the reading of signals stored at that address, control the erasing of signals already stored at that address, and control the writing of new signals. be.

In other words, in order to store a digital signal corresponding to the tuned tuning voltage, the control device sets the storage circuit to the writing state, drives the counter as described above, and when a certain station is received, the counter is activated. is stopped, and the switch for specifying the address is operated to drive the control device and determine the address of the memory circuit.

Thereafter, a switch for storing the output of the counter is operated to drive the control device, erasing the signal already stored at that address, and storing the output of the counter.

To select a channel after storing it in this way, set the storage circuit to the read state by the control device and operate the switch that specifies the address. A signal is read out and set in a counter, and the channel corresponding to the signal can be received.

However, there are certain problems in actually applying such a storage circuit control device to a television receiver.

In other words, from an economic point of view, it is preferable to integrate the control section into an integrated circuit, but this is accompanied by technical difficulties.

That is, although it is preferable to use a non-volatile integrated circuit, it is difficult to actually integrate this circuit together with the control section on the same substrate.

Furthermore, even if the storage section and control section are separated and integrated into an integrated circuit, the signal for generating the channel selection voltage and the signal for specifying the address of the storage circuit will require a considerable number of bits, so in order to output these to the outside, it is necessary to integrate the circuit. The number of pins in the circuit increases, resulting in higher costs.

Furthermore, in order to simplify operation, it is necessary to reduce the number of external control signals as much as possible, generate control signals within the integrated circuit, and operate them step by step. It takes a considerable amount of time for the internal operation of the integrated circuit to complete after the operation, and if a new command is input before the operation is completely completed, the stored contents may be destroyed.

Such accidents are caused by discharge inside the cathode ray tube, chattering of switches, etc.

This invention was made in response to the above points, and even when the storage section and the control section are integrated into separate circuits, the number of pins can be reduced, and control inside the integrated circuit is also easy with a simple circuit configuration. It is an object of the present invention to provide a memory circuit control device which can perform the following operations, and which can also use control signals for other purposes within the integrated circuit to block undesirable external signals.

A memory circuit control device according to the present invention will be described in detail below with reference to the drawings.

FIG. 1 is an overall block diagram of the electronic channel selection device.

The entire block can be further broadly divided into two parts surrounded by dotted lines.

One is the control section 1 and the other is the storage section 2.

These control section 1 and storage section 2 are each configured as separate integrated circuit elements.

The control section 1 has as many channel selection input terminals ch1, -chn as the number of channels required, and these input terminals ch1 to chn are led to the input latch circuit 11.

This input launch circuit 11 is connected to, for example, a channel selection input terminal ch H.
-chn, and is set so that when an input is input to one of the channel selection input terminals ch1 to chn, only the corresponding flip-flop circuit is set.

Therefore, each of the channel selection input terminals ch1 to chn is provided with a switch SW1 that outputs, for example, "0" or "1".

Hereinafter, this switch will be referred to as a channel selection switch.

Each output of each flip-flop circuit is converted by a decoder into a binary signal with the number of bits corresponding to the number of flip-flop circuits, and is applied to the channel latch circuit 12, and the binary signal is set in this channel latch circuit 12. .

The channel launch circuit 12 is composed of an up/down counter.

The channel switching signal generating circuit 13 receives a signal from the channel latch circuit 12, detects a change in the set state of the channel latch circuit 120, generates a channel switching signal, and supplies it to the control circuit 14.

The control circuit 14 generates various control signals using clock pulses and signals applied from other sources.

The operation prohibition signal generation circuit 19 receives the control signal from the control circuit 14 and generates an operation prohibition signal.

The shift register 16 stores a binary signal for generating a channel selection voltage, and the number of bits thereof is equal to the number of bits of the stored binary signal.

The channel selection voltage generation circuit 17 is configured as described above, and receives the binary signal stored in the shift register 16 or internally drives a counter to generate a pulse voltage with a varying duty and performs channel selection. Pulse voltage output terminal vTP
Guided to (.

The pulse voltage present at the output terminal VTP is converted into direct current by a low-pass filter 51 and applied to an electronic tuning tuner 52.

The binary signal stored in the shift register 16 is either a signal to be stored in the storage circuit 21 of the storage section 2, which will be described later, or a signal read out from the stored signal.

That is, when a new signal is to be stored in the storage circuit 21, the control circuit 14 receives the channel switching signal and changes the shift register in order to send out the binary signal stored in the shift register provided in the channel launch circuit 12. During the existence period of clock pulses equal to the number of bits, a signal is output to open the clock pulse input gate of this shift register, and at the same time, the switching gate 15 is output to the channel latch circuit 12 until all the binary signals are sent out.
Outputs an open signal to the side.

Therefore, a binary signal is sent to the storage section 2.

This binary signal becomes a signal that determines the address of the memory circuit 21, and will be described in detail later.

Furthermore, after that, the control circuit 14 receives a storage command signal outputted by the storage instruction cooling signal generation circuit 18 in response to the input applied to the storage terminal M, and generates a control signal to send out the binary signal stored in the shift register 16. Output.

That signal causes a period of existence of clock pulses equal to the number of 160 bits in the shift register 1.
6 is opened, and at the same time, the period switching gate 15 is opened to the shift register 16 side.

As a result, a binary signal is sent from the input/output common terminal 110 to the storage section 2.

These control signals output by the control circuit 14 are generated by converting clock pulses (clock pulses from one clock pulse generation source that are commonly used in each shift register) to various timings using a frequency divider, counter latch circuit, etc. These signals are used as gate signals for the clock pulse input gate of the shift register 16, as signals for switching the switching gate 15, and as signals for driving a memory circuit 21, which will be described later.

Therefore, by appropriately combining these control signals and applying them to the operation prohibition signal generation circuit 19, the operation inhibition signal generation circuit 1
9, an operation prohibition signal can be easily generated.

Further, such control signals are encoded and output from output terminals co, C1, and C2, for example.

A clock pulse is output from the terminal Ck.

As described above, since the control circuit 14 can generate various signals with predetermined timing, it is possible to determine the address of the memory circuit 21, transmit the signal accumulated in the shift register 16, and write this signal to the memory circuit 21. You can have it all done automatically by operating the channel selection switch, but if you do it this way, first press the channel selection switch SW.
If you want to select the channel selection voltage, that is, the channel number after determining the position 1, you will not be able to do so.

Therefore, if the operation of storing data in the memory circuit 21 is performed by external control, it is possible to provide more variety in writing operations.

For this reason, the embodiment shown in FIG. 1 includes a storage terminal M and a storage command signal generation circuit 18.

This terminal M is provided with a switch SW2 whose output is switched to rljrOJ, and this switch SW2 is called a memory switch.

The control section 1 further includes a remote control signal generation circuit 2.
0, and outputs a pulse that drives the counter of the channel latch circuit 12 in response to a signal applied to the remote control signal input terminal R.

Furthermore, it has a write/read switching signal input terminal W/R for switching the operation of the control circuit 14 between a so-called write operation for storing a signal in the memory circuit 21 and a so-called read operation for reading a signal from the memory circuit 21. ing.

This terminal W/R is also provided with a switch SW3 for switching the output to rlJroj, and this switch SW3 is called a write/read changeover switch.

The storage unit 2 includes a control circuit 22 that receives a signal from the control unit 10 control circuit 14, converts it into a control signal, and outputs the signal.

That is, the control circuit 22 connects the terminals C6' and c from the control section 1 to the terminals C6' and c.
1' and c2' are encoded and converted into control signals.

That is, when writing a signal to the memory circuit 21, if the signal that enters the input/output common terminal ■/α is a signal that determines an address, this signal is written to the address register 2 during its existence.
4, the clock pulse input gate of the address register 24 is opened during the period in which there are clock pulses of a number equal to the number of 240 bits of the address register 24, and the switching gate 23 is closed to the address register 24 side during that period. Outputs a control signal to open the gate.

Note that the number of 240 bits in the address register is equal to the number of bits in the address signal.Also, if the signal entering the input/output common terminal 10' is a signal (information signal) for generating a channel selection voltage, the bits in the transfer register 25 During the period when the number of clock pulses equal to the number of clock pulses exists, the clock pulse input gate of the transfer register 25 is opened, and a control signal is outputted to open the switching gate 23 to the transfer register 25 side during that period.

Note that the number of 250 bits in the transfer register is equal to the number of bits of the information signal.

The control signal for controlling as described above is sent from the control circuit 14, and is the same as the control signal for controlling the shift register, switching gate 15, and shift register 16 of the channel latch circuit 12.

These control signals cause address signals to be stored in the address register 24 and information signals to be stored in the transfer register.

Furthermore, the control circuit 22 receives a signal from the control circuit 14 of the control unit 10 and outputs a signal for erasing the signal already stored at the address of the storage circuit 21 determined by the signal stored in the address register 24. , further outputs a signal for writing the signal stored in the transfer register 25 into the storage circuit 21, sequentially adds these signals to the storage circuit 21, and stores the information signal at a predetermined address in the storage circuit 21.

When reading a signal from the memory circuit 21, first, as described above, a signal is output that causes the address signal sent to the input/output supply terminal 110' to be accumulated in the address register 24, and the address signal is accumulated. Furthermore, the memory circuit 21
outputting a signal for reading out the information signal stored in the storage circuit 21, transferring the information signal to the transfer register 25, and furthermore, a period of existence of a clock pulse equal to the number of bits of the transfer register 24; Transfer register 24
It outputs a signal to open the clock pulse input gate of , and closes the switching gate 23 for that period, and simultaneously applies these signals to the transfer register 25 and the switching gate 23 to transfer the information signal.

These signals output by the control circuit 22 are the same as those generated by the control circuit 14 of the control section 10 and are used as they are.

A timing chart of these signals is shown in FIG.

The overall operation will be explained based on this figure. Thereby, the time course of the operation at each stage can be easily understood.

First, the case where a signal is stored in the storage circuit 21 will be described.

In this case, the write/read changeover switch SW3 is switched to write.

In this operation, the storage command signal generation circuit 18 of the control circuit 14
The control circuit 14 does not operate because only the gate provided on the signal input line is opened.

Next, the counter of the channel selection voltage generation circuit 17 is driven to change the channel selection voltage and receive a predetermined channel.

As a result, two communication signals corresponding to the selected channel voltage are simultaneously set in the shift register 16.

Next, operate the channel selection switch at a position different from the position at which reception has been received up to now.

As a result, two communication signals corresponding to the channel selection switches are launched into the channel latch circuit 12, and simultaneously stored in a shift register provided in the channel latch circuit 12.

At this time, a change in the contents of the channel launch circuit 12 is detected by the channel switching signal generating circuit 13, and a channel switching signal shown in FIG. 2 is applied to the control circuit 14.

The gate of the control circuit 14 is opened by this channel switching signal, and the clock pulse shown in FIG. The signal shown in FIG. 2C is generated by this latch circuit.

This signal opens the clock pulse input gate of the shift register provided in the channel latch circuit 12, and the switching gate 15 also opens the clock pulse input gate of the shift register provided in the channel latch circuit 12.
At the same time, the switching gate 23 of the storage section 2 is opened to the address register 24 side, and the clock pulse input gate of the address register 24 is opened.

The shift register of the channel latch circuit 12 and the address register 24 are both driven by the clock pulse shown in FIG. 2A during the signal period of FIG. 2C, and the address signal is stored in the atlus shift register 24.

Next, when the storage switch SW2 is operated, a storage command signal shown in FIG. 2d is applied from the storage command signal generation circuit 18 to the control circuit 14.

The gate of the control circuit 14 is opened by this storage command signal, and the clock pulse shown in FIG. The signal shown in FIG. 2e is generated by this latch circuit.

This signal opens the clock pulse input gate of the shift register 16 and opens the switching gate 15 to the shift register 16 side, and at the same time opens the switching gate 23 of the storage section 2 to the transfer register 25 side to clock the transfer register. A pulse input gate is opened.

As a result, both the shift register 16 and the transfer register 25 are driven by the clock pulses shown in FIG. 2a during the signal period shown in FIG. 2e, and information signals are stored in the transfer register 25.

The control circuit 22 of the storage section 20 outputs the signal shown in FIG. 2f from the fall of the signal shown in FIG. 2e.

This signal is applied to the memory circuit 21 as a signal for erasing the memory contents of the memory circuit 21, and erases the memory contents.

Since the memory circuit 21 is non-volatile, the signal shown in FIG.

Further, the control circuit 22 generates the signal shown in FIG. 2g from the falling edge of the signal shown in FIG. 2f.

This signal is applied to the memory circuit 21 as a signal for writing the information signal stored in the transfer register 25 into the memory circuit, and the information signal is written into the memory circuit 21.

The signal shown in FIG. 2g also requires a period of existence comparable to that of the signal shown in FIG. 2f.

This completes the operation of storing the signal in the memory circuit 21.
Next, the operation of reading signals from the memory circuit 21 will be described.

In this case, the write/read switch SW3 is switched to read.

Next, operate the channel selection switch at a position different from the position where reception has been received up to now.

As a result, the address signal is accumulated in the address register 24 as in the case of writing.

Next, the control circuit 14 counts the clock pulses shown in FIG. 2A for a predetermined period from the fall of the signal shown in FIG. The signal shown in Figure 2 is generated and added to the storage circuit 21, and the information signal stored at the designated address is transferred to the transfer register 25.

Furthermore, the control circuit 14 is set by the next clock pulse of the falling edge of the signal shown in the second figure, and then
A latch circuit that is reset by the 64th pulse generates the signal shown in Figure 2i.

This signal causes the switching gate 15 to switch to the shift register 16.
At the same time, the switching gate 23 is closed, and the clock pulse input gates of the transfer register 25 and shift register 16 are opened, and the clock pulses shown in FIG. information signals are stored.

According to this information signal, the tuning voltage is generated by the tuning voltage generation circuit 1.
7. Electronic tuning tuner 5 made of low-pass filter 51
2, and a channel corresponding to the selected channel voltage is received.

As described above, the storage circuit control device according to the present invention performs two operations during writing: pressing the channel selection switch to determine an address, and pressing the memory switch to store information.
In order to carry out the operation in steps, the signals shown in FIG. 2C, for example, which are generated by the control circuit 14 at the beginning of each step, and the signals shown in FIG. In addition to the prohibition signal generation circuit 19, if the operation prohibition signal generation circuit 19 is configured with a latch circuit that is set, for example, at the rising edge of the first pulse and reset at the falling edge of the first pulse, the output of the launch circuit can be activated. It can be a prohibition signal.

Also, when reading out, press the channel selection switch and read out.
To carry out the operation in steps, the signal shown in FIG. 2C and the signal shown in FIG. 2i may be applied to the operation inhibit signal generation circuit 19.

While the operation prohibition signal is being generated, all flip-flop circuits of the input latch circuit 11 are reset, the operation of the remote control signal generation circuit 10 is stopped, the operation of the channel switching signal generation circuit 13 is stopped, and the storage command signal is The operation of the generating circuit 18 may be stopped.

That is, by providing this operation prohibition signal generation circuit 19, the channel selection switch SW1 or the memory switch SW2
Even if the channel selection switch SW1 or the memory switch SW2 is newly operated during the transfer of an address signal to the memory circuit 21, the transfer of an information signal, or the signal processing such as erasing, writing, reading, etc. Input can be prohibited to prevent malfunctions.

Further, if these switches are mechanical switches, even if chattering occurs during operation and causes malfunction, the operation prohibition signal generating circuit 19 can prevent malfunction due to chattering.

As described above, in the storage circuit control device of the present invention, the storage section and the control section are configured with separate integrated circuit elements, and the storage section and the control section are provided with registers having the same number of bits for address and information, respectively. When these registers are set with binary signals, they are transferred in parallel, and when transferred to other registers, they are transferred in series.Furthermore, the transfer times of address signals and information signals are staggered by switching gates 15 and 23. Since it is controlled, signals can be exchanged through one line connecting the input/output terminals 110° and 10', and the number of pins can be significantly reduced.

In addition, the control signal can be easily created by simply processing clock pulses in various ways, and furthermore, this control signal automatically prohibits input while the internals are in operation, resulting in extremely stable operation. A storage circuit control device can be provided.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment in which a memory circuit control device according to the present invention is applied to an electronic channel selection device of a television receiver, and FIG. 2 shows signals of each part of the block diagram shown in FIG. 1. This is a timing chart. 11... Single car latch circuit, 12... Channel latch circuit, 14... Control circuit, 16
,24゜25...Shift register, 19...
...-operation prohibition signal generation circuit, 21...-memory circuit.

Claims (1)

[Scope of Claims] 1. A storage circuit control device for writing an information signal for controlling the operation of a controlled device into a storage circuit so that it can be stored, and controlling the stored information signal so that it can be read. a control circuit that generates a control signal for performing signal processing; an information signal generation circuit that generates the information signal used to control the operation of the controlled device; and a selection that selects the operation of the controlled device. a switch; an address signal generation circuit that generates an address signal in response to the operation of the selection switch; and a first shifter that stores the address signal and transfers the address signal under the control of a control signal from the control circuit. a latch circuit having a register; a second shift register that stores the information signal and transfers the information signal under the control of a control signal from the control circuit; a second shift register that stores the address signal transferred from the latch circuit and transfers the information signal; a third shift register for determining an address of the storage circuit; and a third shift register for storing the information signal transferred from the second shift register, and transferring the information signal to the second shift register under the control of a control signal from the control circuit. a fourth shift register that transfers the information back to the shift register; and a fourth shift register that is controlled by a control signal from the control circuit and transfers the information signal stored in the fourth shift register to an address determined by the address signal of the storage circuit. a control circuit for a storage circuit configured to write and store information signals and read out the stored information signals to a fourth shift register; a transfer of an address signal from the latch circuit to the third shift register; one line serving for the transfer of information signals between the second shift register and the fourth shift register; gating means for controlling the time of transfer of each signal through the line; and gate means for controlling the time of transfer of each signal through the line; an operation prohibition signal generation circuit that determines a signal processing status and generates a signal that prohibits the operation of the address signal generation circuit and the information signal generation circuit during signal processing for writing to and reading from the storage circuit. A memory circuit control device consisting of: 2. The controlled device is a tuner that can select any channel by applying a tuning voltage to a variable reactance element and changing the tuning voltage, and the information signal is based on the tuning voltage of each channel. 2. The storage circuit control device according to claim 1, wherein the signal corresponds to a channel selection switch, and the selection switch is a channel selection switch.