JPS5816498B2 - Power supply method for multiprocessor processing system - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention improves system reliability in a power supply system for a multiprocessor processing system, particularly in a multiprocessor processing system in which multiple central processing units share multiple groups of peripheral devices. In order to achieve the The present invention relates to a power supply system for a multiprocessor processing system configured to allocate divided auxiliary power supply units to each unit and receive power from a plurality of mutually independent AC power sources.

In order to improve the reliability and processing capacity of data processing systems, multiple central processing unit systems and multiple groups of peripheral equipment systems are combined, so that even if one central processing unit system goes down, other central processing units Efforts have been made to enable backup by multiple systems, or to enable parallel processing by multiple central processing unit systems.

In the case of this system configuration, one central processing unit system bus line and one peripheral device system bus line are connected at their intersection to execute processing.

However, in such a system configuration, if there is a failure in one central processing unit system, one peripheral device system, or a failure in the switching device itself that turns on and off the intersection, operation in other healthy systems will be interrupted. Consideration must be given to ensuring that there are no undesirable effects on the condition.

The present invention aims to solve the above points,
The switching devices installed at each of the above intersections are configured so that they can be controlled independently of each other, and the power to each of the switching devices and other component units including microprocessors can be supplied from an auxiliary power supply unit, and the system is redundant. The purpose of this invention is to provide a main power source for the configuration, prevent system failure due to power failure, and then individually shut off power to the auxiliary power supply units as necessary.

To this end, the power supply system of the multiprocessor processing system of the present invention is such that a plurality of central processing unit systems and a plurality of groups of peripheral device systems use a switching device to switch each central processing unit system bus line and each peripheral device system bus line. In a multiprocessor processing system that is linked by turning on and off through
Switching devices are provided corresponding to the intersections of the central processing unit system bus lines and each peripheral device system bus line on each side and are controlled independently from each other, and the plurality of switching devices and a power supply control management section are provided. The configuration processing device includes a main power unit that receives AC power from multiple independent systems and converts each into DC, and a DC power supply of each main power unit. A processor located in the power supply control management unit, configured to include a power supply relay unit having outputs connected in parallel, and a plurality of auxiliary power supply units to which the outputs from the power supply relay unit are respectively distributed and supplied with power. A configuration is configured such that power is supplied to the device including the plurality of auxiliary power supply units from the plurality of auxiliary power supply units, and at least one of the auxiliary power supply units is individually assigned to the husbands and wives of the plurality of switching devices to supply power from the auxiliary power supply units. It is characterized by what it did.

This will be explained below with reference to the drawings.

FIG. 1 is a configuration of an embodiment of a multiprocessor processing system to which the present invention is applied, FIG. 2 is a block diagram of an embodiment of the constituent processing device shown in FIG. 1, and FIG. 3 is a power supply control system according to the present invention. FIG. 4 is a power supply system diagram of one embodiment of the management section, FIG. 4 is a power supply system diagram of one embodiment of the configuration processing device, and FIG. FIG. 6 shows a power supply system diagram of one embodiment of the connection switching section shown in FIG.

In FIG. 1, 1-1 to 1-m are the central processing units, 2-1 to 2-m are the central processing unit system buses, and 3
-10,3-11.3-20.3-21.・・・・・・
3-m073-ml are central processing unit system channels, 4
-10 to 4-np are peripheral device channels, 5-
1 to 5-n are peripheral device system bus lines, respectively, 6-1 to 5-n are peripheral device system buses, 7 is an auxiliary input/output crab unit, and 8
represents the configuration processing device, and Sw1□ and Ship■ represent the switching devices, respectively.

In the case of the present invention, in order to improve the reliability of the system, there are Switching devices SW, , . . . , 5Wrn n are provided.

Each of the switching devices SW1□ to SWmn is configured to operate independently of each other and is supplied with power from an auxiliary power supply unit that can be turned on and off independently of each other.

The central processing unit 1-1 constitutes one central processing unit system together with the channels 3-10 and 3-11 connected to the bus 2-1, and similarly, the central processing unit i - m constitutes 11 central processing unit systems together with channels 3-mo and 3-ml.

For example, when the central processing unit 1-1 is linked to any one peripheral device system, for example 6-1, the switching device SW,
1 is turned on and processing is executed.

When the processing is finished, the central processing unit 1-1 switches to the switching device S.
W.

The peripheral device system 6-1 is disconnected by switching the power on to the off state.

Needless to say, the ON/OFF state for the switching device SW, ,
The off state is managed by, for example, a configuration control device (not shown) so as not to conflict with control by other central processing units.

, FIG. 2 shows a block diagram of an embodiment of the configuration processing device shown in FIG. 1.

Reference numeral 8 in the figure. SW, , SWmn respectively correspond to those shown in FIG.
11 is a status monitoring unit that performs status monitoring control including turning on and off of the power supply unit of each part and the power status of each part; 12 is a part that enables turning on and off of SWmn; Status display section and switching device 5W
1 indicates the on or off status of Ii to SWmn, and 13 is a power control unit that performs power control for each peripheral device system and channels connected to each central processing unit system bus. things, 14
-81 is an external device power control unit, which is a peripheral device system bus 5.
-1 connected to channel 4-10 or 4-1 p
14-B2 is an external device power supply/control unit that controls power for channels 4-20 to 4-2p connected to the peripheral device system bus 5-2, etc. ..., 14-Cm is an external device power control unit that controls power for channels 3-mo, 3-ml, etc. connected to the central processing unit system bus 2-m, 15-L15-2 16-0, 16-11, . . . are main power supply units that obtain DC voltage from mutually independent input AC 100V power supplies, respectively.
..., 15'=mn represent auxiliary power supply units that supply power to each section including the switching devices SW1□ to SWmn.

In order to improve system reliability, the configuration processing unit 8 has a redundant main power supply 15-L15-2 powered by mutually independent input AC 100V power supplies,
It is equipped with an auxiliary power supply unit that can independently turn on and off each part including the cutter switching device Sw1 and the cutter switch SWmn.

If it is necessary to disconnect the switching device Sw1□ from the system for some reason, the auxiliary power supply unit 1
6-11 is disconnected from the power supply system.

Each of the switching devices SW1□ to SWmn is controlled to be turned on or off by the corresponding central processing unit as described above with reference to FIG. be able to be controlled.

For example, if a failure occurs in the central processing unit 1-1, the switching devices SW1□ to SW,n are controlled to be in an OFF state and disconnected from the system as necessary.

For example, if a failure occurs in the peripheral device system 6-1, the switching device 8-1 or SWm1 is controlled to be in an OFF state and disconnected from the system as necessary.

Further, for example, in the case of a failure in the switching device Sw1□ itself, the switching device SW,1 is disconnected from the system by controlling the auxiliary power supply unit 1611, etc.

The on or off state of each switching device SW1 to SWmn is displayed by the status display section 12.

Needless to say, the status monitoring unit 11 receives the status of each central processing unit system, the status of each peripheral device system which is also notified by the illustrated power supply control unit 13, the status of each power source, etc., and detects failures as necessary. control to deal with this.

FIG. 3 shows the configuration of an embodiment of the power supply control management section according to the present invention.

Symbols in the diagram: 4, 10° 1L 12, 13, 14, 15, 1
6 corresponds to FIGS. 1 and 2.

17 is the power supply control management department, and 18 is the microcontroller.
22-1.22-2. processor; 19, power control unit; 20, remote control power control unit; 21, auxiliary input/output crab unit power control unit; 22-1.22-2. . . . - represents a channel, and 23 represents an input/output control device.

The status monitoring unit 11 is provided with a stored program controlled processor 18, which controls a power supply control system.

As explained with reference to FIG. 2, the status monitoring unit 11 stores the status of the power supply of each unit on a management table (not shown), and is notified by an interrupt when a status change occurs in the power supply of each unit. be done.

Then, depending on whether the state change is a major failure or not, in the case of a major failure, processing such as power shutdown is executed, for example.

The general management device 19 is a main power supply unit 15-1 or 15-
2 status and auxiliary power unit) 16-0, 16-1
1, . . . -16-mn, and directly controls them.

In addition, the power status of the central processing unit system and peripheral equipment system is
The power supply control unit 14 of each section notifies the supervisory management device 19 via the supervisory management auxiliary device (power supply control unit) 13.

Further, the power supply control section 14 for each section is controlled via the overall management auxiliary device 13.

Furthermore, the power supply control section for the auxiliary input/output crab knit is also controlled via the overall management auxiliary device 13, and its status is monitored.

Further, a remote control power supply control section 20 is connected to the general management auxiliary device 13, and on/off control signals for each power source from the host device are notified to the general management device 19 via the general management auxiliary device 13.

In the illustrated power supply control management unit 17, as a control system, the management device 19 directly controls and monitors the status of the auxiliary power supply unit 16, etc., and the power management auxiliary device 13 intervenes to control and experience the peripheral equipment system. Monitoring is separated into a hierarchical structure.

The control and status monitoring of the peripheral equipment system and the like is assigned to the overall management auxiliary device 13 to some extent.

However, it goes without saying that a direct route ROUTE may be created between the power control unit and any power control unit, for example 14-Bl, to directly notify the supervisory control device 19 of changes in status.

The power supply system will be explained below with reference to FIGS. 4 to 6.

In FIG. 4, the symbols 9, 11.13, 15-Li2-
2 and 16 correspond to FIGS. 2 and 3.

24-1 and 24-2 are transformer units each receiving power from independent AC power sources and absorbing the phase difference between the mutually independent AC power sources;
is a power supply relay unit and is connected to the main power supply unit N5-1 or 1.
A device that connects and distributes the DC output from 5-2 in parallel, 2
6 is a diode, 27 is a transformer, 28 is a capacitor,
29 represents a switch.

The power relay unit 25 connects two main power units)
The voltage received via 15-1 and 15-2 and converted to direct current is distributed to each component unit and also supplied to the plurality of auxiliary power supply units 16.

Power is supplied to the status monitoring unit 11 and the general management auxiliary device 13 from a plurality of auxiliary power supply units 16, so as to achieve uninterrupted power supply.

Further, a plurality of auxiliary power supply units 16 are connected to the connection switching section 9, and each switching device 81 to S in the connection switching section 9
For example, one auxiliary power supply unit 16 corresponds to Wmn.
are associated.

Then, in response to a failure of one switching device 5Wij, the power of the switching device 5Wij is cut off and the switching device SW is switched off.
i j is caused to be disconnected from the system.

FIG. 5 shows a power supply system diagram of one embodiment of the state monitoring unit 11 and the supervisory control auxiliary device 13 shown in FIGS. 3 and 4. In FIG.

Codes in the figure 10.1L12.13, 14, 16, 18,
19,20°21 correspond to FIG.

30-030-1 is a common memory, and 31-A is a common memory.
31-B is a power status monitoring unit that monitors the status of the AC voltage from the main power unit N5-1, and 31-B is a power status monitoring unit that monitors the status of the AC voltage from the main power unit 15-2. It represents.

The illustrated microprocessors #IMPCA, #2MPCA, and #I5PCA execute power supply control, and are supplied with power from, for example, two auxiliary power supplies 16.

Also shown #OCOM, #I COM (301°30-
1) is a common memory in which control programs and the like are stored.

Furthermore, in the general management auxiliary device 13, the IPSD (31
-A, 31-B) are the main power supplies 15-1 and 15-, respectively.
The AC power reception status with 2 is monitored.

FIG. 6 shows a power supply system diagram of one embodiment of the connection switching section shown in FIG.

The figure is shown corresponding to one block belonging to the connection switching section BO3U shown in FIG. 4, and it may be considered that the connection switching section BO8U includes a plurality of blocks as shown in FIG. 4.

Reference numeral 16 in the figure represents an auxiliary power supply unit, especially 16
-11 is the auxiliary power supply unit corresponding to the changeover switch SW1, ...16-14 is the changeover switch 5W1n
It represents the auxiliary power supply unit corresponding to (SW, 4').

Further, 32 corresponds to a changeover switch sv adapter, 33 corresponds to a bus control adapter, and 34 corresponds to a changeover switch status monitoring adapter.

As explained above, according to the present invention, in a multiprocessor processing system in which a plurality of central processing unit systems share a plurality of groups of peripheral device systems, switching that can be controlled independently from each other at positions corresponding to intersections of bus lines is provided. In addition to creating a device history, an auxiliary power supply unit is assigned to each component unit in the configuration processing unit so that it can be disconnected from the system by turning off the power individually, and especially important component units can be disconnected from the system. For this purpose, the auxiliary power supply units are duplicated to achieve uninterrupted power supply.

Furthermore, the AC power receiving system is duplicated to ensure power supply within the configuration processing device.

For this purpose, system failures caused by power failures can be almost certainly prevented, and component units that are at risk of affecting other units due to failures caused by the central processing unit, peripheral equipment, or switching equipment themselves can be completely prevented. It is possible to disconnect from the system regardless of the

The power supply system can be monitored by stored program control, and processing to deal with failures can be executed completely automatically.

[Brief explanation of drawings]

FIG. 1 is a configuration of an embodiment of a multiprocessor processing system to which the present invention is applied, FIG. 2 is a block diagram of an embodiment of the constituent processing device shown in FIG. 1, and FIG. 3 is a power supply control system according to the present invention. FIG. 4 is a power supply system diagram of one embodiment of the management section, FIG. 4 is a power supply system diagram of one embodiment of the configuration processing device, and FIG. FIG. 6 shows a power supply system diagram of one embodiment of the connection switching section shown in FIG. In the figure, 1 is the central processing unit, 2 is the central processing unit system bus line, and 3
is the central processing unit channel, 4 is the peripheral device channel,
5 is the peripheral device system bus line, 6 is the peripheral charge system, S field 1 to S
Wmn is a switching device, 8 is a configuration processing device, 9 is a connection switching section, 11 is a status monitoring section, 13 is a power supply control section (supervision management auxiliary device), 14 is an external device power supply control section, 15 is a main power supply unit, 16 is an auxiliary power supply unit, 17 is a general management unit, 18 is a microprocessor, 19 is a general management unit, 2
4 is a transformer unit, 25 is a power relay unit, 3
0 represents common memory.

Claims (1)

[Claims] 1. In a multiprocessor processing system in which a plurality of central processing unit systems and a plurality of groups of peripheral device systems are linked by turning each central processing unit system bus line and each peripheral device system bus line on and off via a switching device. , switching devices are provided corresponding to the intersections of the central processing unit system bus lines and each peripheral device system bus line on each side and are controlled independently from each other, and the plurality of switching devices and power supply control management are provided. The configuration processing device includes a main power supply unit that receives alternating current power from multiple independent systems and converts it to direct current, and It is configured to include a power supply relay unit having DC outputs connected in parallel, and a plurality of auxiliary power supply units to which the output from the power supply relay unit is distributed and supplied with power, and is located in the power supply control management unit. A device including a processor is supplied with power from the plurality of auxiliary power supply units, and at least one of the auxiliary power supply units is individually assigned to the husbands and wives of the plurality of switching devices to supply power from the auxiliary power supply unit. A power supply method for a multiprocessor processing system characterized by the following configuration.