JPS58159169A - Parallel processing system - Google Patents

Abstract

PURPOSE:To improve the parallelism without enlarging the scale of a memory switch, by converting the processors taking charge of the parallel processing into parallel processing processors consisting of plural processor elements. CONSTITUTION:Each of processors PP1'-PP16' performs the reading/writing to an optional one of data memories DM1-DM32 via a memory switch MS. A control processor CP contains memories CPM1 and CPM2 exclusive for control and can give an access to the memories DM1-DM32 via the switch MS. Furthermore the processor CP can have communication with each processor via an interface (a) and a control processor interface CPI' of each of processors PP1'-PP16'.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical field to which the invention pertains] The present invention relates to a parallel processing method, and particularly to a parallel processing method in a data processing device.

Generally, one of the methods for speeding up arithmetic processing is a parallel processing method.

This parallel processing method executes parts of the program that can be executed in parallel using different processors, and N
Ideally, the goal is to obtain N times the performance with one processor (actually, parts that cannot be executed in parallel, extra time for rounding to control parallel operations, etc., overhead... (For this reason, the performance is only N times lower.) [Prior art] The conventional parallel processing method consists of a control processor, a plurality of data memories each storing data, and a control processor connected in parallel to the control processor. a plurality of connected processors; and a memory switch for interconnecting the plurality of processors and the plurality of data memories in parallel, each of the plurality of processors having a processor element;
The processor is configured to include an 1tlJ (i141 processor interface) for connecting the processor element to the control processor, and a memory switch interface for connecting the processor element to the memory switch.

Next, a conventional parallel processing method will be explained in detail with reference to the drawings.

FIG. 1 is a system configuration diagram showing an example of a conventional parallel processing system, and FIG. 2 is a detailed block diagram showing an example of the processor shown in FIG. 1.

The parallel processing system shown in FIG. Shi9'' memory MMI~MM32
and a memory switch having 16×32=512 connection points for mutually connecting 16 processors and 32 memories in parallel.

All of the processors PPI to PP16 have the same configuration and, as shown in FIG. 2, include a processor element PE, a memory switch interface M8, and an I control processor interface CPI. Memory interface M8I is processor Nilemen) PH
A rounding access request for data flow or program continuation is sent to the memory MMI via the memory switch MS.
~Supply to MM32 and memo IJMMI~MM3
The data read from the processor element PE is supplied to the processor element PE, and the data read from the processor element PE is supplied to the memory MMI-MM32 to be stored therein. The control processor interface CPI is connected to the control processor CP via the interface at-, and receives program execution start instructions 5TART and program execution stop instructions 5TOP from the control processor CP, and supplies them to the processor elements PW, and also supplies them to the processor elements PW. A processing end notification gND is supplied to the control processor CP.

That is, 16 processors PPI to PP16 are connected to 32 memories MMI to MM3 via memory switch M8.
2, each processor P
P1 to PP16 can each independently execute programs. Control processor CP is processor PPI
- It supplies a program execution start instruction 5TART'i through the interface a with the PP 16, and receives a processing end notification END when the processor has completely completed execution.

Under the control of this control processor CP the processor PPI
-PP15 share and execute the parallel processing part in the program to be solved. For example, al+bl, al
+bl, -...1 am+bn, the i-th processor PPi calculates al-1-bi.

In order to improve the performance of such conventional parallel processing systems, it is necessary to increase the performance of each processor or increase the number of processors.

However, increasing the performance of the processor increases the size of the device, making it difficult to arrange a large number of them. moreover,
When the number of processors increases, the memory must also be expanded to be able to use memory in parallel.1Memory switches increase in size by the product of the number of processors and the number of memory, making them complex and large-scale. It will still be difficult to realize (for example, considering a crossbar switch, if you double the number of processors and the number of memory, the scale of the switch will be 2X
2 = 4 times). Because of these drawbacks, large-scale, ultra-high-performance parallel processing systems are rarely put into practical use.

That is, the conventional parallel processing method has a drawback in that it is difficult to increase the degree of parallelism.

[Purpose of the invention]

An object of the present invention is to provide a parallel processing method that can increase the degree of parallelism.

That is, an object of the present invention is to solve the above-mentioned drawbacks by increasing the degree of parallelism without increasing the scale of the memory switch by making each processor that shares parallel processing into a parallel processing processor consisting of a plurality of processor elements. We are a company that provides parallel processing systems with large-scale, ultra-high performance.

[Structure of the invention]

The parallel processing method of the present invention is based on a control processor.

a plurality of data memories each storing data; a plurality of processors connected in parallel to the control processor; and a memory switch for mutually connecting the processor of the Waki and the data memory of the Ling in parallel. Each of the plurality of processors includes a plurality of processor elements provided in parallel, a program memory that is provided in common to each processor element and stores a program, and the control processor of the plurality of processors. and a memory switch interface for connecting the plurality of processor elements to the memory switch.

In other words, the parallel processing method of the present invention allows each data memory access to be performed from among a plurality of processor elements, a program memory shared by the plurality of processor elements, and data memory access requests generated from the plurality of processor elements. A memory that enables access from any of the above-mentioned arithmetic processing units to any of the above-mentioned data memories, including several arithmetic processing units w consisting of a circuit that selects and processes one at each timing, a plurality of data memories, and a circuit that selects and processes one at each timing. and a switch.

Furthermore, in addition to the above configuration, the parallel processing method of the present invention has the following features:
A control processor, comprising a control processor, four means for instructing all of the processor elements to start program execution from the control processor, and a flat membrane for notifying the control processor of the end of program execution from each of the processor elements, and under the control of the control processor. The parallel processing portion of one program is configured to be executed in parallel (by all the processor elements).

In other words, in the parallel processing method of the present invention, by configuring each processor that handles parallel processing with a plurality of processor elements that operate in parallel, the actual number of parallel processing processors can be increased without increasing the scale of the memory switch. There is.

That is, the parallel processing system of the present invention has n processors, m data memories, such as n or 2n data memories, these n processors, m data memories, and 1: nxm connected rounded continuation points t4
The internal structure of one processor of each of these n 10 processors is implemented by one processor element, and the memory shared by these four processor elements is used to execute one processor element. The memory switch interface includes one program memory that stores a program to be executed, and a memory switch interface that receives and processes access to the m data memories from each of the four processors. In other words, this memory switch ink-face is activated at every memory access timing! One of the access requests from any of the i+1 processor elements on the ground is selected, and the selected access request is sent to the data memory via the memory switch. If this access request is a read request, the data sent from the data memory is passed to the requesting processor. in this way,
Memo IJ With the switch interface, data memory access □,< Since the interface is integrated into one, the current number of memory switches (number of interfaces for connecting processors) can be set to tl/J.

In this case, access to data memory competes between one processor element, which may become a performance bottleneck, but the problem is that programs dedicated to programs shared by one processor element are
This is reduced by having Moriwo. In other words, in a normal computer, programs and data are stored in the same memory, but in the processor used in the present invention, programs are stored in a dedicated program memory, so access to the memory is not possible through the memory switch interface. The access frequency is limited to data, and the access frequency is reduced to at most 1/2 compared to a normal computer.

[Explanation and explanation of examples]

Next, embodiments of the present invention will be described in detail with reference to the drawings.

Figure 3 is a system configuration diagram showing one embodiment of the present invention;
The figure is a detailed block diagram of the processor shown in FIG. 3.

The processors PPI' to PP16' have a parallel processing system including eight processors PH1 to PE8, each having the ability to execute eight programs in parallel. However, the number of processors and the number of processor elements therein are not limited to this example.

Each processor PPl/~PP16/ is a memory switch M
Data can be sequentially output and written to any data memory DM1-DM32 via S. The number of data memories is 32 in Figure 3, but this depends on the number of processors, the performance of the data memory, and the use of data memory #5.
It is determined by 1 degree and is not limited to this example.

Further, there are many configuration methods for the configuration of the memory switch MS, including a complete configuration and a loss bar type, but the configuration is not limited to any one of them.

Here, as an example, it is assumed that a complete crossbar system is used, and even if a plurality of processors simultaneously request access to the data memory, no contention will occur between accesses to the same data memory. Even if a memory switch MStl having another configuration is used, the effect of the present invention is not affected.

The control processor CP has a control-only memo 1. ICPMI.

CPM2, and can also access data memories DMI to DM32 via memory switch M8.

Although the number of control-only memories is two in this example, it is not limited to this. The control processor CP connects each processor PP1' to PP15 via an interface f.
' respective control processor interface CPI
'can communicate with each processor via '.

FIG. 4 is a block diagram showing an example of the processor shown in FIG. 3.

Each of the processor elements pgi to PE8 has the ability to execute a program, and the program is stored in a dedicated program memory PM commonly connected to the processor elements PEI to PE8. The program memory controller PMC controls access to the program memory PM, and controls traffic control for access from the processor elements PE1 to PEs.

The memory switch interface MSI' is a control circuit for each processor element PE1 to PE8 to access the data memories DM1 to DM32 shown in FIG.
When there are access requests from multiple processor elements PFJ1 to PE8 at the same time, one of them is selected according to a certain algorithm, and the selected access request is sent to the data memory DMI via the memory switch MS.
~ DM32. In the case of a read operation, control is also performed to deliver the data sent from the corresponding data memory to the requesting processor element according to the sent address.

The control processor interface CPI' is a circuit for communicating with the control processor CP, and controls the communication between each processor element Pgl to PE8 and the control processor 02, as well as the communication between the processors PP1' to PP16' themselves and the control processor 02. In this method, each processor element PR1 to Pg8 is visible to the software.
Since the processors PPI' to PP16' have meaning only as a physical unit (device unit), communication with the control processor CP is logically mainly between the processor element and the control processor 02).

As an example of this communication, each processor element PE1~
Program execution start instruction 5TART, which instructs PE8 to start program execution, and program execution stop instruction 5T.
There are OPs etc. Processor elements PE1 to PE8
starts executing the program upon receiving the program execution start instruction 5TART, and stops the operation when a predetermined condition is met or when the program execution stop instruction 5TOP is received. First, the control processor interface CPI also performs rounding mY@ to transmit information from the processor elements PFlt to PE8 to the control processor CP via the interface f. For example, after receiving the program execution start instruction 5TART and starting execution, It is also the control processor interface CPI' that notifies the controlling processor P when the elements PEI to PB8 have completed their execution.

Each processor is different in that it is read from the configuration of Pg1 to PE8. In a general computer, instructions and data are stored in the same memory, but in the parallel processing system using the present invention, rounding instructions to reduce the load on access paths to the data memory IJc) Ml to C) MB2 are stored in the program memory. It is stored in ljPM4-M#. This is the data for each processor Nilemen) P'BI ~ PE8
Since it is necessary to transfer data between the processors PPI/~PP16', it has to be stored in a common data memory, but the program does not need to do this, and It utilizes the property that it can be stored in a dedicated memory that is shared by the elements pgt to PJlim8 but provided for each of the processors PP11 to PP16'.

The valley processor elements PE1 to Pg8 repeat the operation of reading data from the data memories DMI-DM32, processing them, and returning the results to the data memories DM1 to DM32 according to the program stored in the program memory PM.

In the parallel processing system shown in FIG. 3, the operation when executing a program is as follows.

Shimegeru.

Before starting the calculation, the data Ai and Bi are controlled by the processor CP.
is stored in the data memories DM1 to DM32. for example,
Data person 1~A mouth is data A9~ in data memory DM1
A! * is stored in the data memory lJDM2, and data A4w to A1g are stored in the data memory DM161 in the same manner. Similarly, data Bl-B is data memory DM
I7, data B, ~B1m are stored in the data memory DM18, . . . data Bl)O~Bit1 are stored in the data memory DM32.

In this example, there are 16 (number of processors) x
8 (number of processor elements in each processor) = 1
Of the 28 processor elements, the li-th processor element Pgi calculates A1XB1 and stores the calculation result 01 in the data memory. The program for performing this FtF calculation is the processor elements PEI to PE8.
is stored in the program memory PM common to
The instruction address register in each processor element PE1 to PE8 is
Program memo of the first instruction word to be executed by E8 1. I
The PM address is set. This is the control processor C
Data memory DMI ~ ball 32 to memory switch MS and memory switch interface M8 under the control of P
I' or 6 or interface 8
and through the control processor interface CPI'.

The control processor CP performs the above preparations, and once completed, it issues a program execution start instruction 8TAl- to all 128 processor elements through the interface at-.
LT t-processor PPI' to PP16'iC is sent. This allows all processor elements Pg
1 to PB8 retrieve, decode, and execute an instruction word from the program memory PM according to the value of each instruction address register.

Now, processor element P in processor PPI'
Taking g1 as an example, calculate A,
1 in the data memory.

Similarly, the processor element PE2 calculates A and XB values and stores the calculation result C3, and the processor element PE8 similarly processes A@XA@→C8. These processes are carried out by each processor element Pg1.
~pgs run concurrently in parallel.

Although the program is assumed to be executed, it may be a different program, or even if the program is the same, if a conditional branch is inserted, there is a possibility that each processor element will execute a different instruction sequence from the middle. .

Here, the programs stored in the program memory PM will be briefly explained.

There is no particular problem if the program stored in the program memory PM is different for each processor element PE1 to PE8, but if one program is shared by all processor elements PE1 to PE8, it is possible. Therefore, special measures are required. The operation of arithmetic processing such as addition and multiplication and its II order are common to each processor element PR1 to PE8, and the data stored in the data memories DMI to DM32 used are different for each processor element PE1 to PE8. It is from. For this purpose, for example, index registers are used to store the operands of the instruction words in the program.
Possible options include modifying the address and using it. For example, in the case of the command "Add the data at address A to the achiemulator", each processor element Pg1 to Pg8
stores the processor element honorary number riJt in its own index register, and when executing the above instruction r, modifies the address At- with the index register and reads 11+tJ.
All you have to do is add the address data to the Akyemulator. This allows the processor elements PEI to PE8 to all perform the same addition operation, but use different data.

Access requests from each processor element PR1 to PE8 to each data memory IJDM1 to DM32 (Ai, Bi
Requests to read C4 and store C4 are traffic-arranged by the memory switch interface MSI', and if there is a conflict, only one is selected and the others are put on hold.
The timing of instruction execution of each processor element PE1 to PE8 may be shifted. Similarly, competition occurs between the processor elements PK1 to PR8 regarding access to the program memory PM, but the program memory controller PMC, which is a control unit of the program memory PM, coordinates traffic.

Therefore, even if the same program is executed, all processor elements pgi to PE8 do not perform the same operations and processes at the same time in complete synchronization.

When the processing of the arithmetic processing AtxBs-+cs is completed, the control processor CP is notified of this through the control processor interface CPI' and the interface a. The control processor CP waits for completion notifications from all 128 processor elements PB1 to PE8 and then executes ΣCi.
process. Since the calculation results sst and the results Ci are stored in the data memories IJDMI to DM32, the control processor OP switches the memory switch M8.
The data memos IJDMI to DM32 are accessed via the data memos IJDMI to DM32 and the calculation results CI are added in the order of reading. This operation is the same as addition in a general compiler, and the control processor CP
By the program inside, the calculation result CI + CI +・
...Sequentially read and add to CIM1. When this addition is completed, the desired answer is obtained.

Notifications from each processor element Pgl to PE8 to the control processor CP may be sent to the control processor CP every time each processor element PEI to PE8 completes as described above, but they are grouped within the processors PPI' to PP16'. It may be possible to reduce the number of exchanges with the control processor CP by notifying the processor CP.

Alternatively, instead of having the control-1 processor CP execute all of the Iit calculations of ΣCi as described above, a method may be considered in which the processor elements PE1 to PE8 perform part of the calculation.

That is, for example, cl+c, +...+C may be executed as follows in the processor PPI'. (C
, 10C) + (Cm+C4)r (Cs+C5)r(
Cy+Cs) are performed in parallel using t-4 processor elements PE1 to PE8, and the results are calculated as DI+D! + D sudden + D4, then (
Ds+Ds) + (DI+D4)e performed in parallel,
Letting the results be B t and E y respectively, finally B
I+E Calculate snow. Each processor PPI'
~ If it is done within PP16', the control processor CP only needs to calculate the sum of the 16 operation results left by the 16 processors PP1' to PP16' (in the previous example, the control processor CP performs 127 additions). (This method only requires 15 additions).

Which method to use for calculation is entirely controlled by the glogram, so it is up to the user's choice.

In this way, in the embodiment shown in FIG. 3, 128 parallel operations can be performed by 16 processors PP1' to PP16' each including eight processor elements PHI-PE8, but in reality, 128 independent processors are used. For example, the scale of the memory switch MS would be 128x32, but in this example it is only 16x32, which is advantageous in terms of device implementation (cost).

(in terms of device size, performance, etc.).

〔Effect of the invention〕

In the parallel processing method of the present invention, each of the processors connected in parallel to a control processor and connected to each other in parallel via a plurality of data memories and memory switches operates in parallel instead of each consisting of a single processor element. By providing multiple processor elements in parallel,
When viewed from the memory switch side, it appears that the memory switch has only a single processor element, but since a plurality of processor elements can be connected to the memory switch in a time-sharing manner, the effect of increasing parallelism can be realized.

In other words, the parallel processing method of the present invention facilitates the realization of parallel operations with a large degree of parallelism by configuring a processor parallel system that includes a plurality of processor elements to operate in parallel under the control of a control processor. Parts that cannot be computed in parallel are processed by a control processor, which has the effect of increasing flexibility and expanding the field of application.

[Brief explanation of drawings]

FIG. 1 is a system configuration diagram showing a conventional example, FIG. 2 is a detailed block diagram of the processor shown in FIG. 1, FIG. 3 is a system configuration diagram showing an embodiment of the present invention, and FIG. FIG. 2 is a detailed block diagram of the processor shown in the figure. cp...Control processor, PPI to PP16
, PPI/~PP 16'...processor,
CPMI, Cf'M2... Control dedicated memory, M
8...Memory switch, MMI to MM32...
...Memory, M8I, M8I'...Memory switch interface, CPI, CPI'...River...
Control processor interface, pg, pEt to PE
8... Processor Niremen), DM1 to DM3
2...Data memory, PM...Program memory, PMC...Program memory controller, a...Interface. 1st question Pth? garden

Claims (1)

[Claims] a control processor, a plurality of data memories each storing data, a plurality of processors connected in parallel to the control processor, and a rounding circuit interconnecting the plurality of processors and the plurality of data memories in parallel. each of the plurality of processors includes a plurality of processor elements provided in parallel, a program memory that is provided in common to each processor element and stores a program, and a memory switch that connects the plurality of processor elements to the memory switch. A parallel processing method comprising: a control processor interface for connecting to a control processor; and a memory switch interface for connecting the plurality of processor elements to the memory switch.