JPS58158751A - Detecting method of anomalous state of computer - Google Patents

Abstract

PURPOSE:To detect an anomalous state by high performance, by comparing a processing mode deciding data with a processing end bit data, stopping a clear signal to a counter in case of dissidence, and detecting an abnormal state of a program processing condition, etc. CONSTITUTION:A processing mode deciding pattern data MPD for deciding a processing condition which processes a program by a microcomputer 1 is provided to a latch gate 7, and when each program ends, a processing end bit data PFB is provided to a latch gate 6. Also, when processing of a series of programs ends, a counter clear signal CCS is applied to an output buffer gate 2, outputs of the gates 6, 7 are compared by a comparator 8, and in case of coincidence, an output of the comparator 8 and the clear signal CCS from the gate 2 are applied to an AND gate 10, and an output of the gate is provided as a clear signal to a counter 4 for counting an output of an oscillator 3. In case of dissidence of the result of comparison, the clear signal applied to the counter 4 is stopped, and an anomalous state of the program is detected.

Description

[Detailed Description of the Invention] +8) Description of Technical Field The present invention relates to abnormality detection in microcomputers, and relates to a technology for detecting abnormalities in patented program processing.

(bl Description of Prior Art) In conventional computers, in order to detect abnormalities in the processing state, both software and hardware are used.
Various methods are used, but one known method is to install a hardware timer called a watchdog timer (hereinafter abbreviated as π) outside the computer to monitor the program while it is being processed. ing.

Figure 1 is a block diagram showing the configuration of an abnormality detection device when detecting an abnormality in the processing state using the above-mentioned WDT.
The oscillator 3 is independent of the operation of the microcomputer 1.
Pulse oscillation continues as long as the system power is supplied. This oscillation output is counted by a counter 4, and when a predetermined number is reached, an output is generated. The output signal of the counter 4 is outputted via the buffer 5 and becomes an alarm signal or a command signal for backup processing or the like. The program in the microcomputer 1 is released 412 as shown in the flowchart shown in FIG. 2, for example, and when the series of processing is completed, a counter clear signal is outputted via the output buffer gate 2.

If the time required for the count value of color 4 to go from 0 to overflow and output is set to be greater than the maximum time required to execute a series of processes, the microcomputer 1
As long as the counter 4 is normal, a clear signal is always output before the output of the counter 4 is generated, and no alarm signal is generated.

FIG. 3 is an explanatory diagram of the operation of the abnormality detection device shown in FIG.
(a) shows the counter clear signal output from the microcomputer 1, (b) shows the pulse oscillation output of the oscillator 3, the count data counted by the counter 4 as an analog value, and (clii the alarm signal of the counter 4) This is what is shown.

The reason why the intervals of the counter clear signals in Figure 3 are not constant is that
This is because the time required to complete a series of processes differs depending on the program processing conditions.6 As shown in point (d) in Figure 3, if the program processing time is abnormally longer than the predetermined value, this is detected. Performs backup processing such as stopping the microcomputer 1.

The watchdog timer method described above is a method that has been widely used in the past, but it simply monitors whether the program processing time remains within a predetermined time, so it is difficult to determine the program processing order. Or, even if an abnormality occurs in the conditions such as permission or prohibition of program processing itself, if the processing time is within a predetermined value, the abnormality cannot be detected, or if the processing time is abnormally short. Similarly, it has the essential drawback of not being able to detect abnormalities.

Ic) Purpose of the Invention The present invention has been made in view of the above-mentioned points. To provide a highly functional abnormality detection method for a combiator for abnormalities under conditions of permission and prohibition.

1dl Configuration of the Invention The configuration of the present invention will be described below with reference to the drawings.

FIG. 4 shows a block diagram of an embodiment of the abnormality detection device for a microcomputer according to the present invention.1. Ta.

Figure 4 - 'c', l#i In the microcomputer, processing mode determination pattern data MPD for determining the processing conditions for program processing is sent to the latch gate 7, and processing end bit data indicating the end of the processing program at the end of each processing program. PFB is output to the latch gate 6, and a counter clear signal CC8 is output to the output buffer gate 2 when a series of program processing is completed.

The outputs of the latch gates 6 and 7 are input to a comparator 8, and when these two inputs match, the output of the comparator 8 and the counter clear signal CC8 outputted from the microcomputer 1 via the output buffer gate 2 are sent to A.
10 and counted by the counter 4, the pulse output of the energizer 3 is cleared by the output of the AND gate 10.

If the counter 40 count is not cleared, the counter 4 generates an output and outputs it to the outside via the buffer 5 as an alarm signal.

(el) Function of the Invention An embodiment of the present invention shown in FIG. 4 will be described below.

First, the processing flow of this embodiment will be explained with reference to FIG. In a first step 21 of the process, process conditions are determined. The program modules to be executed and the modules not to be executed are determined in advance according to the conditions, and those to be executed are designated as 11 @ l, those that are not are designated as Iol, and the program modules are installed internally in the microcomputer 1 or in a do-on memory ROM (
Not shown. ) is stored as processing mode determination pattern data MPO, and a pattern matching the conditions is selected from this data and outputted via the latch gate 7 shown in FIG. Next, in steps 22 to 27, the module to be processed is determined according to the processing conditions and the program processing is executed, and processing end bit data P indicating the end of processing only when executed in each module program.
FB is output from the latch gate 6 shown in FIG. The processing end bit data PFB output is all retained at the end of the series of processing.

Next, in step 28, a counter clear signal CC8 for clearing the count value of the counter 4 shown in FIG. 4 is outputted via the output buffer 2.

Repeat the above process.

FIG. 6 shows an example of the processing mode determination pattern data MPD stored in the read-on memory (not shown) built into the microcomputer 1 shown in FIG. 4, in which the number of processing programs is 8. This is an example of a case. In processing mode 1, all program processes 11) to 18) are executed, and in processing mode 2, programs (2) and (4) are executed.
, (51 passes the process.

Details of the comparator 8 shown in FIG. 4 are shown in FIG. 7.

Processing mode determination pattern data MPDt is input from part (a) as 18-bit data, and processing end bit data PFB indicating the end of processing of each program is output to lines (1) to (8) corresponding to that program. do. That is, when a series of program processing is completed, the processing end bit data PFB is output to the line corresponding to the busy processing program of each of (1) to (8). For example, in processing mode 3 shown in Fig. 6, (11, (2, +61, (
7), each line of (8) [#'i"l' is (3).

(IQI is output to each line 41 and +51.

In the processing flow shown in FIG. 5 already explained, considering the case of processing mode 3 shown in FIG. 6, if the operation of the microcomputer 1 is normal, the processing mode determination pattern data MPD ' 11100
011" is input to the comparator 8, and when the series of processing is completed, the processing end bit data PFB output is "
11100011" Input signal to Natsu Y comparator 8.

When the two input data to the comparator 8 are different, the output of the comparator 8 is J@ and k. At the final step 28 of the processing flow shown in FIG. , the output of the AND gate 10 shown in FIG. 4 becomes 111, and the counter 4 is cleared.

As described above, as long as the operation of the microcomputer 1 is normal, the counter 4 is cleared every cycle and no plum signal is generated.

For example, an abnormality occurred in the microcomputer 1 due to a hardware problem such as a memory, a program bit error noise, etc., and in one case, the processing program (2) in step 24 shown in FIG. 5 that should have been processed was not processed. In this case, the processing mode determination pattern data MPD for processing mode 3 shown in FIG. 6 is '11100011.
' fArno[L[End hit data PFB is "111
00001".

A mismatch occurs between the two inputs to comparator 8.

Therefore, the counter clear signal CC8 of the counter 4 is not permitted, and the counter 4 continues counting until it reaches a predetermined value. Output.

The above description has been made regarding the path w6c in which the abnormal mode is one process, but it is clear that the same detection is possible for the execution of a program that does not require processing, since the two inputs to the comparator 8 do not match.

In the embodiment described above, the processing mode determination pattern data M
Comparison of PD and processing end bit data PF'B is performed by a comparator configured with hardware, but this comparison process is programmed and processed within a microcomputer, and a counter clear signal is issued only when the permission condition is met. It is also possible to configure it to output.

(f) Detailed Description of the Invention According to the present invention, the program passes processing contrary to conditions, executes unnecessary processing, runs out of order, or conditions such as permission or prohibition of program processing itself. If an abnormality occurs in the system, it is possible to detect this and issue an alarm, commands for backup processing, etc. Even if the processing time is abnormally short, the abnormality can be detected in the same way. function can be obtained.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of a conventional abnormality detection device, and FIG. 2 is a diagram showing an example of the process 70- in FIG. 1. Figure s1 is an operation explanatory diagram, Figure 4 is a diagram showing an embodiment of the abnormality detection device of the present invention, Figure 5 is a diagram showing an example of the processing flow of Figure 4, and Figure 6 is Figure 4. A diagram showing an example of the memory state of W. FIG. 7 is a diagram showing some details of FIG. 4. 1... Microcomputer 2... Output buffer gate 3... Oscillator 4... Counter 5... Insulated buffer gate 6... Latch gate 7... Latch gate 8... Comparator (7317) substitute Person Patent Attorney Noriyuki Chika (and 1 other person) 1st v! J Figure 2 Figure 3 Figure 4 Figure 5

Claims (1)

[Claims] The output pulses of the oscillator are counted and timed by a counter, and at the end of each cycle of program processing, the computer outputs a count value clear signal to the counter to compare the passage of time, and the program processing time is determined as the predetermined time. In a computer abnormality detection method that outputs an abnormality signal when an abnormality signal is exceeded, the processing mode is determined by comparing processing mode determination pattern data that determines the processing conditions for program processing in the computer with processing end pit data that indicates the end of each processing program. A method for detecting an abnormality in a computer, comprising blocking the clear signal to the counter when pattern data and processing end bit data do not match.