JPS58147809A - Recording and reproducing circuit of data signal - Google Patents

Abstract

PURPOSE:To obtain an accurate data signal without reference to the wow and flutter of a recording and reproducing device by putting a data signal and clock pulses together and recording them on a signal track, and then separating its reproduced signal into a reproduced data signal and reproduced clock pulses. CONSTITUTION:The clock pulses (a) and data signal (b) are ANDed by an AND gate circuit G, whose output (c) is supplied to an adder AD, the output (d) of which is passed through a low-pass filter LPF to obtain an output (f) from which higher harmonic components are removed. Consequently, a modulator MOD imposes frequency modulation on a carrier fc of audio frequency to obtain a recording signal SR with a narrow frequency band, thereby allowing the recording and reproducing device to perform recording to a single track freely. After the recording signal SR is recorded by the recording and reproducing device, its reproduced signal SP is separated into the clock pulses and the reproduced data signal is sampled.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides a recording and reproducing method that records a data signal and a clock pulse on a single track of an audio recording and reproducing device, and extracts a reproduced data signal and a reproduced clock pulse from a reproduced signal. It is related to circuits.

When data signals are recorded using an audio recording/playback device (hereinafter referred to as a recording/playback device) such as a cassette tape recorder, the recording and playback conditions become unstable due to the wow/wow characteristics of the recording/playback device. , a clock pulse is simultaneously recorded along with a data signal, and the reproduced data signal is sampled using the reproduced clock pulse to obtain an accurate data signal, but conventionally, the data signal and clock pulse are recorded on each individual track. This has the drawback that a recording/reproducing device having only a single track, such as a monaural recording/reproducing device, cannot be used.

The present invention has an object of fundamentally eliminating the drawbacks of the conventional art, and has a simple structure, combines a data signal and a clock pulse, records it on a single track, and then uses the reproduced signal from the synthesized data signal and clock pulse. The present invention provides an extremely effective data signal recording and reproducing circuit that separates a reproduced data signal and a reproduced clock pulse.

1 is a block diagram of a recording circuit, and FIG. 2 is a timing chart showing waveforms of each part in FIG. 1. The data signal (b) is given to the AND gate G as a gate circuit, where the logical product of both is extracted and becomes the output (c), and the adder A
given to D.

On the other hand, the clock pulse (-) is generated by the level shift circuit LS.
%H# (
%L# (low level) becomes a negative potential output (d), which is then applied to the adder, and as a result of the addition, the data signal (d) becomes Immediately after changing from " to 1LI, the potential is zero, and the other parts are converted into an output (.) that repeats positive potential and negative potential.

Therefore, if this is taken out via the P-wave reducing device LPF, the output (f) from which harmonic components have been removed will be obtained.
Frequency modulation by OD results in a recording signal Sm with a narrow frequency band, which allows recording on a single track of a recording/reproducing device.

Note that since the recording signal Si has a narrow frequency band, even if the frequency response characteristics of the recording/reproducing device are not good, the recording signal Si
When reproduced, the amplitude characteristics of the reproduced signal are good.

FIG. 3 is a block diagram of the reproducing circuit, and FIG. 4 is a timing chart showing the waveforms of each part in FIG. The frequency is detected and demodulated to output (a), which undergoes level slices in both positive and negative directions in a level slicer L8C consisting of an amplifier and a 5-pin, and output (b), which is then sent to the first and second comparators. given to CP& + CFx.

In addition, the comparator CPs is given a positive reference voltage +E as one polarity, and the comparator CP! A negative reference voltage -E is given as the other polarity, and the output (bit) and (d) are produced only when a level higher than this reference voltage is given. Only components with positive polarity are extracted from the comparator CPz, and only components with negative polarity are extracted from the comparator CPz.

Therefore, if the rising edge of the output (,) drives a pulse generator PG such as a monostable multivibrator and generates a pulse signal (.) with the same width t as the data signal (b) in FIG. This becomes the reproduced data signal DP. On the other hand, the output (a) has the same waveform as the clock pulse (a) in Figure 2, but with %H' and 'L# inverted, so it is sent to the inverter IN. If it is inverted and output (f), the reproduced clock pulse CKP will be exactly the same as the clock pulse (a) in FIG. 2.

Therefore, if the reproduced data signal DP is sampled at the falling edge of the reproduced clock pulse CKP, an accurate data signal can be obtained regardless of the wow and flutter of the recording/reproducing device. Circuit L
The direction of the level shift by SF may be determined according to the polarity of the output (c), and depending on the frequency response characteristics of the modulator MOD, the low-pass P wave filter LPF t may be omitted, and the AND gate G may be omitted. The same applies to 't-NAND game 1.

Furthermore, in FIG. 3, the inverter IN may be omitted and the output (.) may be sampled by the rising edge of the output (a), and the present invention can be modified in various ways. As described above, according to the present invention, data signals and clock pulses can be completely recorded using only a single track by a relatively inexpensive recording and reproducing device with many wow and flutters, and the data signals and clock pulses can be completely recorded using only a single track. Since the regenerated clock pulse can be easily obtained, it can be used for various types of data! 0, which has a remarkable effect when recording and reproducing signal tubes.

[Brief explanation of the drawing]

The figures show an embodiment of the present invention, FIG. 1 is a block diagram of a recording circuit, FIG. 2 is a timing chart showing waveforms of each part in FIG. 1, FIG. 3 is a block diagram of a reproducing circuit, and FIG. This is a timing chart showing the waveforms of each part in FIG. 3.OG...AND gate (gate circuit), LSF...
・Level shift circuit, AD...adder, MOD...
... Modulator, DEM ... Demodulator, LSC ... e-level slicer, CPs ... First comparator, CP
Liao: Second comparator, PG: Pulse generator, D: Data signal, CK: Clock pulse, SR: Deployment signal, 8P: Regeneration signal, D
r...Reproduction data deni, CKp...Reproduction clock pulse.

Claims (1)

[Claims] a gate circuit that extracts a logical product between a data signal and a clock pulse; a level shift circuit that applies a level shifter to the clock pulse to a polarity opposite to the polarity of the signal at the output of the gate circuit; and the level shift circuit. an adder that adds the output of the gate circuit and the output of the gate circuit; a modulator that performs frequency modulation on a carrier wave using the output of the adder and sends it out as a recording signal; a demodulator that performs demodulation on the output of the demodulator; a level slicer that performs level slicing in both positive and negative directions on the output of the demodulator; a first comparator that extracts a component having one polarity from the output of the level slicer; a second comparator that extracts a component with the other polarity from the output of the level slicer and sends it out as a reproduced clock pulse; and a pulse signal having the same width as the data signal according to the output of the first comparator. 1. A data signal recording/reproducing circuit comprising: a pulse generator for transmitting the signal as reproduced data.