JPS58147288A - Differential encoding system - Google Patents

Differential encoding system

Info

Publication number
JPS58147288A
JPS58147288A JP57030031A JP3003182A JPS58147288A JP S58147288 A JPS58147288 A JP S58147288A JP 57030031 A JP57030031 A JP 57030031A JP 3003182 A JP3003182 A JP 3003182A JP S58147288 A JPS58147288 A JP S58147288A
Authority
JP
Japan
Prior art keywords
signal
circuit
conversion circuit
converted
differential
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP57030031A
Other languages
Japanese (ja)
Inventor
Yoshiji Nishizawa
西沢 美次
Koichi Oota
幸一 太田
Makoto Hiraoka
誠 平岡
Toshio Hanabatake
花畑 利男
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP57030031A priority Critical patent/JPS58147288A/en
Publication of JPS58147288A publication Critical patent/JPS58147288A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04NPICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N23/00Cameras or camera modules comprising electronic image sensors; Control thereof
    • H04N23/80Camera processing pipelines; Components thereof
    • H04N23/84Camera processing pipelines; Components thereof for processing colour signals

Abstract

PURPOSE:To use a low speed differential encoding circuit, by differentially encoding a color signal A/D-converted by a frequency having n-times the subcarrier frequency at every (n-1) sets of the said color signal. CONSTITUTION:The color signal is sampled with a frequency n.fsc (in this case, n=3) having n-times the subcarrier frequency fsc of the said color signal and converted into a digital signal at an A/D conversion circuit 1. This signal is converted into a parallel signal at a series/ parallel conversion circuit 2. This parallel signal is inputted to the 1st, the 2nd, and the 3rd differential encoding circuits 3, 4 and 5 corresponding to the combination for differential operation. The signal differential-encoded and outputted sequentially are outputted to a transmission line 10 via a P/S conversion circuit 8 and a transmission line encoder 9.

Description

【発明の詳細な説明】 (1)  発明の技術分野 号化方式に関す。[Detailed description of the invention] (1) Technical field of the invention Regarding the encoding method.

(bJ  iE米技術と問題点 力y−v!に微信号を帯域圧縮して伝送するに際し、該
カラーvlkiIl!信号(以下カラー信号と紀す)の
すプキャリアの2倍以上の周波数で該カラー信号をサン
プリングしてA/D変換し、該A/D変換されたカラー
信号を差分符号化して力2−信号の帯域圧縮を行ってい
る。
(bJ iE US technology and problems When transmitting a weak signal with band compression to y-v!, the color vlkiIl! signal (hereinafter referred to as color signal) is transmitted at a frequency that is more than twice that of the main carrier. The color signal is sampled and A/D converted, and the A/D converted color signal is differentially encoded to perform band compression of the power 2 signal.

しかし、該カラー信号が鳥解m度l1iIiJXの場合
、該カラー信号は広帯域テレビ信号となシ、この様なな
広帯域テレビ信号の帯域圧縮を従来の差分符号化回路で
行うとサンプリング周波数が高くな9、該力2−信号の
相an合う夫々の信号の差分演算が技術的に困難になる
However, when the color signal has a bird's resolution l1iIiJX, the color signal is not a wideband television signal, and if the band compression of such a wideband television signal is performed using a conventional differential encoding circuit, the sampling frequency will be high. 9. It becomes technically difficult to calculate the difference between each of the force 2-signals that match each other.

(C)  発明の目的 本発明は上記の問題点を解決するために、サブキャリア
fcのnXfcO周波数でA/D変換され友カラー信号
を該カラー信号の(n−1)債おきに差分符号化する新
規な差分符号化方式を提供することを目的とする。
(C) Object of the Invention In order to solve the above-mentioned problems, the present invention performs A/D conversion at the nXfcO frequency of the subcarrier fc and performs differential encoding on every (n-1) color signal. The purpose of this study is to provide a new differential encoding method.

(dJ  発明の構成 この目的のために本発明は力2−妖像信号のサブキャリ
ア周波数のn倍の周波数で該力2−映像信号をサンプリ
ングしてA/D変換する手段を有し、該A/D変換され
た該カラー映倫信号を(n−1)個おきに差分符号化す
る手段を有し、腋差分符号化されたカッ−映像信号を(
n−1)個おきに復号化することにより達成される。
(dJ Structure of the Invention For this purpose, the present invention has a means for sampling and A/D converting the force 2-image signal at a frequency n times the subcarrier frequency of the force 2-image signal, It has a means for differentially encoding every (n-1) A/D-converted color video signal, and converts the armpit differentially encoded color video signal into (
This is achieved by decoding every n-1) pieces.

−発明の実施例 以下、本発明を図面に基づいて述べる・第1図は本発明
に係る差分符号化方式に用いるn装置きのデジタルカッ
−信号の配置を示す・同図はカラー信号のサブキャリア
周波数facon倍の周波数nXfsc(n:整数)の
サンプリング周波数で69、該テンプリング周波数fs
cでカラー信号をA/D変換したときのデジタルカッ−
信号(以下デジタル信号と記す)を示す・#11図ia
)は該デジタル信号をH−a 3で差分演算を行うとき
の備考関係を示す。図(a)は■の信号と■の信号の差
分を、■の信号と■の信号の差分を順次、差分演算回路
で行う。
- Embodiments of the Invention The present invention will be described below with reference to the drawings. Figure 1 shows the arrangement of digital color signals in a device used in the differential encoding method according to the present invention. The sampling frequency is 69 with a frequency nXfsc (n: integer) that is twice the carrier frequency facon, and the tempering frequency fs
Digital signal when color signal is A/D converted with c
Showing the signal (hereinafter referred to as digital signal)・#11Figure ia
) indicates the relationship to be noted when performing a differential calculation on the digital signal using H-a 3. In Figure (a), the difference between the signal ``■'' and the signal ``■'' is sequentially calculated by a difference calculation circuit.

第1図(b)は上記0n−5の場合を示す・図(b)は
■の信号と■の信号との差分を、■の信号と■の信号と
の差分演算を行う。
FIG. 1(b) shows the case of 0n-5. In FIG. 1(b), the difference between the ■ signal and the ■ signal is calculated, and the difference between the ■ signal and the ■ signal is calculated.

いは115豐周し、夫々差分信号に変換することが出来
る。上記の差分演算は次のようにして行う。
or 115 cycles, and each can be converted into a differential signal. The above difference calculation is performed as follows.

すなわちデジタル信号を(n−1)個おきに差分演算を
行えば、該カラー信号を1 / nに分鳩して差分演算
することになる。この様にすれば差分符号化回路の演算
を容易にすることが出来る。
That is, if a difference calculation is performed on every (n-1) digital signal, the difference calculation will be performed on the color signals divided into 1/n groups. In this way, the calculation of the differential encoding circuit can be facilitated.

このために、直列信号の該カラー信号をn列の並列信号
に変換して並列信号間の差分演算を行うことによp前記
カラー信号をn個おきに差分演算することが出来る・ 本発明を上記の原理に基づき第2図の実施例に従って述
べる。同図においてカラー信号のサブキャリア周波数f
acのn倍の周波数n・fsc、(1例としてn−3)
すなわち3 facで該力2−信号をサンプリングして
、A/D変換回路1でデジタル信号に変換する。そのデ
ジタル信号は第111(a)に示す即き■〜■の配置と
なる。この信号を直並列変換回路(以下S/P変換回路
と記す)2で並列信号に変換すると第3図に示す如き配
置となる。
For this purpose, by converting the color signal in the form of a serial signal into n columns of parallel signals and performing a difference calculation between the parallel signals, it is possible to perform a difference calculation for every n color signals. Based on the above principle, the embodiment shown in FIG. 2 will be described. In the same figure, the subcarrier frequency f of the color signal
Frequency n・fsc, which is n times ac (n-3 as an example)
That is, the force 2 signal is sampled by 3 fac and converted into a digital signal by the A/D conversion circuit 1. The digital signals are arranged as shown in No. 111(a). When this signal is converted into a parallel signal by a serial/parallel conversion circuit (hereinafter referred to as an S/P conversion circuit) 2, an arrangement as shown in FIG. 3 is obtained.

この並列信号(■、■、@)、(■、■、■)、(■■
、■)・−・・・・・・・・・・・・・の■と■、■と
■、■と■の組合せで夫々に対応した第1.第2.第3
差分符号化回路3. 4. 5に入力され、差分演算が
行われる・ 減算器6にて差分がとられ、量子化回路7にて量子化さ
れ帯域圧縮信号■r整形される。量子化回路3の量子化
特性については、後記第6図で述べる。該帯域圧縮信号
■牡並直列変換回路(以下P/S変換回路と記す)8に
入力され、伝送路符号ll1I9を経て伝送路10に出
力される。
This parallel signal (■, ■, @), (■, ■, ■), (■■
, ■)・-・・・・・・・・・・・・The first corresponding combination of ■ and ■, ■ and ■, and ■ and ■. Second. Third
Differential encoding circuit 3. 4. The subtracter 6 calculates the difference, and the quantizer 7 quantizes and shapes the band compressed signal ■r. The quantization characteristics of the quantization circuit 3 will be described later in FIG. 6. The band compressed signal is inputted to a parallel-to-serial conversion circuit (hereinafter referred to as a P/S conversion circuit) 8, and outputted to a transmission line 10 via a transmission line code 11I9.

また、帯域圧縮信号■′の一部は加算8611で1信号
前の値と加算演算され、遅延器13で1信号間隔遅延さ
れ、諷′X器6と加算illとに入力される。
Further, a part of the band compressed signal ``■'' is added to the value of the previous signal in the adder 8611, delayed by one signal interval in the delayer 13, and inputted to the inverter 6 and the adder ill.

次に3個おきの並列信号■が減算器6に入力され、遅延
器12に保持された信号■′との差分演算が行われ、差
信号■−■Iが出力され、該差信号■−■Iは量子化回
路7で第4図に示す如く(ユ■す′、に量子化される。
Next, every third parallel signal ■ is input to the subtracter 6, and a difference operation is performed with the signal ■′ held in the delay device 12, and a difference signal ■−■I is output, and the difference signal ■−■ (2) I is quantized by the quantization circuit 7 as shown in FIG.

この後順次、3個おきの信号との差分演算が行われ、量
子化回路7から帯域圧縮信号として出力されP/S 変
換回路8、伝送路符号器9を経て伝送路10よシ受信側
に伝送される。
Thereafter, differential calculations are sequentially performed with every third signal, and the signal is output as a band compression signal from the quantization circuit 7, passes through the P/S conversion circuit 8, the transmission line encoder 9, and then goes to the transmission line 10 on the receiving side. transmitted.

次に並列信号■と■及び■と■の夫々の組の差分演算が
第2及び#!3差分符号化回路4及び5すなをち、減算
器13−量子化回路14−加算器15−遅延器16及び
減算器17−ft子化回路18−加算器19−遅延器2
0にて上記第1差分符号化(ロ)路3と同様の手法で差
分符号化が行われ夫々の童子化回路15.16よシ第4
図に示す如き差分符号化信号として順次出力される。該
出力は&$変換回路8、伝送路符号器9を経て伝送路1
0に出力され受信端局21に伝送される。
Next, the difference calculations for the respective sets of parallel signals ■ and ■ and ■ and ■ are performed in the second and #! 3 differential encoding circuits 4 and 5, namely, subtracter 13 - quantization circuit 14 - adder 15 - delay unit 16 and subtractor 17 - ft childization circuit 18 - adder 19 - delay unit 2
0, differential encoding is performed in the same manner as in the first differential encoding (b) path 3, and the respective doji conversion circuits 15, 16 and 4
The signals are sequentially output as differentially encoded signals as shown in the figure. The output is sent to the transmission line 1 via the &$ conversion circuit 8 and the transmission line encoder 9.
0 and transmitted to the receiving terminal station 21.

第5図は受信端局に伝送されたデジタル信号の加′J#
儂号化回路を示す。同図において、受信端局21の伝送
路符号器22にて伝送路符号信号は帯域圧動された伝送
前のデジタル信号に変換され、該デジタル信号はS/P
変換回路23にて並列信号に変換され、前記の差分符号
化信号になる。前記の並列信号の先頭値■′は第1加算
復号化回路24の加算器25.P/S変換回路26を経
てD/A変換回路27にてカラー信号に変換され、その
一部■′倍信号遅延器28にて1信号間隔遅延され、保
持される。次に3個置の差分符号化回路■−■す′が加
算器25に入力され、遅延器28の出力■′が加算され
元の並列信号■に復号化される。
Figure 5 shows the addition of the digital signal transmitted to the receiving terminal station.
The decoding circuit is shown. In the same figure, a transmission line encoder 22 of a receiving terminal station 21 converts a transmission line code signal into a digital signal before transmission, which has been band-shifted.
The signal is converted into a parallel signal by the conversion circuit 23, and becomes the differentially encoded signal. The leading value ■' of the parallel signal is sent to the adder 25. of the first addition/decoding circuit 24. The signal is converted into a color signal by the D/A converter circuit 27 via the P/S converter circuit 26, and a portion of the signal is delayed by one signal interval by the x' signal delayer 28 and held. Next, the three differential encoding circuits ``--'' are inputted to the adder 25, and the output ``■'' of the delay device 28 is added and decoded into the original parallel signal ``■''.

また、加算tI29、遅延器30よすなる第2加算復号
化回路31及び加算器32、遅延器33よシなる第3加
算復号化回路34においても他の組の並列信号が前記と
同様の手法で帯域圧縮され九デジタル信号を元のデジタ
ル信号に復調する。復調された並列信号FiP/8変換
回路26で直列信号に変換され、D/A変換回路27に
て元の力2−信号に戻される。
Also, in the second addition/decoding circuit 31 consisting of the addition tI 29 and the delay device 30, and the third addition/decoding circuit 34 consisting of the adder 32 and the delay device 33, other sets of parallel signals are processed using the same method as described above. The band-compressed digital signal is demodulated into the original digital signal. The demodulated parallel signal is converted into a serial signal by the FiP/8 conversion circuit 26, and returned to the original power 2-signal by the D/A conversion circuit 27.

前述した童子化回路7.14.18の特性をfg6図に
示す。同図で横軸は入力信号を示し、縦軸は量子化され
た出力信号を示す。図中の数字は10進数で示されてい
る。入力レベル2〜5に対し4如く入力信号が量子化さ
れる。
The characteristics of the aforementioned Doji conversion circuit 7.14.18 are shown in Fig. fg6. In the figure, the horizontal axis shows the input signal, and the vertical axis shows the quantized output signal. The numbers in the figure are shown in decimal notation. The input signal is quantized by 4 for input levels 2 to 5.

(fJ  発明の効果 本発明によれば、デジタルカラー係号を1 / nに分
周して差分符号化が行われるので、差分符号化回路に低
速のものが使用でき該回路のコストを低下できる利点を
有する。
(fJ Effects of the Invention According to the present invention, differential encoding is performed by dividing the digital color coefficient by 1/n, so a low-speed differential encoding circuit can be used and the cost of the circuit can be reduced. has advantages.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明を説明するためのデジタル信号のn分周
を示す図、第2図は本発明実施例の差分符号化回路、第
3図はデジタル信号の並列配置図、第4図は本発明に係
る差分符号化信号、第5図は不発明実施例の差分復号化
回路、第6図は童子化回路の人出力%住を示す。 図中、1はA/D R換回路、2,23はS/P変換回
路、3,4.5は差分符号化回路、b、13゜17は減
算器、7,14.18は量子化回踏、8゜26はP/S
変換回路、9Fi伝送路符号器、10は伝送路、11,
15,19,25,29.32は加算器、12,16,
20,28,30.33は遅延器、21は受信端局、2
2#′J:伝送路復号器、24,31゜34は加算復号
回路、27FiD/A変換回路を示すO −田
FIG. 1 is a diagram showing n frequency division of a digital signal for explaining the present invention, FIG. 2 is a differential encoding circuit according to an embodiment of the present invention, FIG. 3 is a diagram of parallel arrangement of digital signals, and FIG. FIG. 5 shows the differentially encoded signal according to the present invention, FIG. 5 shows the differential decoding circuit of the non-inventive embodiment, and FIG. 6 shows the human output % of the doji conversion circuit. In the figure, 1 is an A/DR conversion circuit, 2 and 23 are S/P conversion circuits, 3 and 4.5 are differential encoding circuits, b, 13° and 17 are subtractors, and 7 and 14.18 are quantization circuits. Round trip, 8°26 is P/S
conversion circuit, 9Fi transmission line encoder, 10 transmission line, 11,
15, 19, 25, 29.32 are adders, 12, 16,
20, 28, 30.33 are delay devices, 21 is a receiving terminal station, 2
2#'J: Transmission line decoder, 24, 31゜34 is addition decoding circuit, 27Fi D/A conversion circuit is shown.

Claims (1)

【特許請求の範囲】[Claims] 力2−跣像儒号のデジタル帯域圧縮伝送方式にグしてA
/Di換する手段を有し、該A/D変換されIt該カラ
ー映書信号を(D−1)@おきに差分符た差分符号化方
式。
Power 2 - A for digital band compression transmission method
A differential encoding method having means for converting the A/D-converted color movie signal into a differential code every (D-1)@.
JP57030031A 1982-02-26 1982-02-26 Differential encoding system Pending JPS58147288A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57030031A JPS58147288A (en) 1982-02-26 1982-02-26 Differential encoding system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57030031A JPS58147288A (en) 1982-02-26 1982-02-26 Differential encoding system

Publications (1)

Publication Number Publication Date
JPS58147288A true JPS58147288A (en) 1983-09-02

Family

ID=12292444

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57030031A Pending JPS58147288A (en) 1982-02-26 1982-02-26 Differential encoding system

Country Status (1)

Country Link
JP (1) JPS58147288A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4924298A (en) * 1987-09-18 1990-05-08 Victor Company Of Japan, Ltd. Method and apparatus for predictive coding
US5103294A (en) * 1987-10-27 1992-04-07 Canon Kabushiki Kaisha Predictive coding system
US5249047A (en) * 1987-10-27 1993-09-28 Canon Kabushiki Kaisha Predictive coding system

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4924298A (en) * 1987-09-18 1990-05-08 Victor Company Of Japan, Ltd. Method and apparatus for predictive coding
US5103294A (en) * 1987-10-27 1992-04-07 Canon Kabushiki Kaisha Predictive coding system
US5249047A (en) * 1987-10-27 1993-09-28 Canon Kabushiki Kaisha Predictive coding system

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