JPS58129842A - Radio selective call receiver - Google Patents

Abstract

PURPOSE:To realize a simple, accurate display test, by equipping a decoder which decodes a local calling number and display information with a control part, when detecting display test patterns, displaying test display patterns automatically and successively. CONSTITUTION:A signal from an antenna 1 is amplified, detected, and demodulated at a radio part 2 and then inputted to a waveform shaping circuit 3. The output of the circuit 3 is inputted to the decoder 4, which compares the local calling number written previously in a P-ROM5 with the signal from the circuit 3 and then allows a speaker 7 to sound through an amplifier 6 when they coincide with each other. On the other hand, when the output of the circuit 3 coincides with a test state setting signal pattern, a display test is performed automatically according to the previously stored display pattern. Therefore, it is unnecessary to change and transmit test patterns several times and the pattern need be sent only once, performing the display test accurately.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field Description] The present invention relates to a wireless selective calling receiver (Pellboy). In particular, the present invention relates to a wireless selective calling receiver with a display function that displays numbers, characters, etc. in addition to the ringing sound on the LODC 1 & crystal display display element.

[Description of prior art]

Conventionally, woodcutter's wireless selective calling receiver with display function (hereinafter referred to as "receiver with display" 2) has been able to detect defects in the display element, defective display element drive channel, or poor contact with Fi. Display tests have been conducted during use to detect. This display test is performed by transmitting required types of test patterns to the signal transmitting side.

For this reason, when there are many 0@ types displayed and the number of test patterns associated with this increases, it becomes necessary to change the encoding of the existing device, and the operating procedure for the test becomes complicated. .

[Explanation of purpose]

The present invention improves the above points, and even when the number of display types increases, display tests can be automatically and easily performed for a large number of patterns, and display tests can be performed accurately. The purpose of this invention is to provide a receiver with a display that can be used.

[Summary of the invention]

The present invention comprises a radio unit that demodulates a received signal, a decoder that decodes a calling number and display information from the demodulated signal from the radio unit, a means for emitting a sound by the output of the decoder, and a display means for visually displaying display information based on the output of the decoder;
The decoder includes a control unit including a microprocessor, and when a display test pattern is detected from the signal received by the wireless unit, the control unit automatically displays the test display pattern on the display means according to a programmed procedure. The 9% room is configured to be displayed sequentially.

[Explanation of Examples]

An embodiment of the present invention will be described based on the drawings.

FIG. 1 is a block diagram of main parts of an embodiment of the present invention.

An antenna 1 is connected to a radio section 2.

The output of this radio section 2 is guided to a waveform shaping circuit 3.

The output of this waveform shaping circuit 3 is guided to a decoder 4. This decoder 4 has a P-ROM (Programma
ble Read ONLY Memory) 5 is connected. The output of this decoder 4 is led to an amplifier 6. The output of this amplifier 6 is guided to a speaker 7. Further, the output of the decoder 4 is led to the LCD 8.

FIG. 2 is a detailed diagram of the decoder 4. As shown in FIG. Decoder 4
It is composed of a Fi1 chip microprocessor (in this case, μPD 7502 G manufactured by Nll0). That is, a control section 11 that controls each section according to the contents of the program memory 10, a program counter 12 connected to the program memory 10, and a module connected to the data bus 13.
14, A OC15, data memory 16, input port 19.20, output port 21.22, data memory 16
A CD controller driver 23, an oscillator 25 to which a crystal 24 is connected, and a timer 26 are formed on one chip.

FIG. 3 is a diagram showing the format of the received signal. In FIG. 3, P is a prefix signal, which is a repeating pattern of "1" and "0". ν is a 7-frame synchronization signal, which is a signal for frame synchronization of each subsequent ringing signal and display information signal.

FIG. 4 is a flowchart showing the operation of a display test which is a feature of the present invention. FIG. 4 shows a state in which a predetermined number of bits of the prefix signal P are detected. Also, in this flowchart, is the frame synchronization signal? When a special pattern is received, the receiver is put into the display test state and a test is performed.

FIG. 5 is a diagram showing an example of a display pattern for a display test. FIG. 5 shows a case where the display pattern has 10 digits, and each pattern is displayed for #it seconds and moves on to the next pattern after 9 seconds.

The reception operation will be explained using such a circuit configuration.

A radio frequency signal from an antenna 1 is amplified, frequency converted, detected, and demodulated in a radio section 2. The demodulated signal is converted by the waveform shaping circuit 3 into a waveform that can be read by the decoder 4. The decoder 4 compares its calling number, which has been written in advance in the #iP-ROM 5, with the signal from the waveform shaping circuit 3. If they match, a ringing signal is sent to the amplifier 6 to notify the user of the call, causing the speaker 7 to ring.

Further, the decoder 4 drives the LCD 8 based on the display information signal following the calling signal N to provide visible information to the recipient. That is, the program memo IJIOK in the decoder 4
A series of operation commands are written in. The operation command stored in the address displayed on the program counter 12 from the program memory 10 is output to the control section 11. Depending on this content, the control section 11 sends control signals to each section.

The program counter 12 normally increases by +1 each time the contents of the program memory 10 are sent to the control section 11. However, it may be rewritten by special commands such as jump commands. Input or output ports (19-22) Fi output or input data between the external circuit and the data bus 13 specified by a control signal from the control unit 11.

Detection of one's own calling number is performed as follows.・In other words, the received signal from the waveform shaping circuit 3 is sent to the input port 19.
is input to the data bus 13 through the decoder 4.
The control unit 11 receives an interrupt at the rising or falling edge of the received signal, and when the command being executed is completed, processing for the interrupt is started. However, it is also possible to inhibit interrupts by an instruction -t'. That is, the control section 11 is periodically interrupted by the prefix signal P having a pattern of repeating 1's and 0's.

Bit synchronization is achieved by synchronizing the output of a timer 20, which receives nine clocks generated by the crystal 24 and the oscillation section 25 and is controlled by the control section 11, with the cycle of this interrupt. When bit synchronization is completed, interrupts from the IME terminal are prohibited.

A predetermined number of bits of the repeated pattern of 1 and O of the previous f signal P are detected, and the process moves on to detecting the frame synchronization signal ν.

A specific pattern is written in the program memory 10 in advance as a frame synchronization code.

After the specific pattern is loaded into the module OO 15, it is stored in the data memory 16 through the data bus 13. Further, the own discharge number is written in the P-ROM 5, and the data of the address addressed by the signal from the calling number output port 22 is input to the input port 20.
The data is loaded into the program CC 15 through the entire data bus 13, and stored in the data memory 16 through the data bus 13. When the timer 26 is out of synchronization with the prefix signal P, the received signal from the input boat 19 is sequentially loaded into the MU 15 and synchronized with the specific pattern of the frame synchronization signal r stored in the data memory 16. are compared.

If a match is achieved within the time corresponding to the prefix signal length p bits+frame synchronization signal length f bits, a match signal is issued from the mu L U 14 and the operation moves on to receive the calling number. (p10f
) If there is no matching signal within the time of the bit, the prefix signal P is sent again.
Return to reception. The same process as the detection of the frame synchronization signal F is performed for the paging signal No. 1 MIIC.

Display information signal engineering is loaded into the program memory 1015, and this data is written into the corresponding program memory 10.

The displayed data is converted into display data of the table contained in the table, and is stored in the data memory 16. The display information signals from the input boat 19 are thus stored in the data memory 16 sequentially. However, this display information signal reception operation is performed only when the own calling number is detected. In this way, the own calling number is detected and the display data is stored in the data memory 1.
6, a tone control signal is output from the output port 21, and the speaker 7 is driven by the amplifier 6 to notify the recipient that there are many calls. In addition, the data memory 16
The display data is converted by the LCD controller driver 23 into a signal that can drive the fi LOD 53, providing visual information to the receiver.

Next, the display test operation, which is a feature of the present invention, will be explained in detail using the flowchart of FIG.

First, in judgment A, it is determined whether the received pattern is a frame synchronization signal, and if it matches a predetermined frame synchronization signal, a paging signal is detected. That is, the receiving operation described above is performed. If the received signal does not match the frame synchronization signal in judgment A, it is compared in judgment B to see if the received signal matches the test state setting signal pattern stored in advance in the data memory 16K in the same way as the frame synchronization signal. If they do not match, after the detection of the prefix signal P (p+r)
Judgment C determines whether the bit time has elapsed. If it is within the time of p+f) bits, continue to judge K.
RD, if the time of (p+f) bits has elapsed, the process returns to receiving the prefix signal P again.

In judgment B, if the received signal pattern matches the test state setting signal pattern, the receiver displays the test pattern shown in FIG. The total number m of display pattern types is set,
The number of display patterns to be displayed on LODg is determined. These m types of test display patterns are stored in the data memo 1716 in advance. The processing MFi determines the display time of one test display pattern, and the processing F
The time t for displaying and holding the test display pattern is determined. The same pattern is displayed until the judgment G makes all judgments after the time t has elapsed. Judgment H after time t has elapsed
Check to see if all test patterns have been completed. If the process has been completed, the display is cleared and the process moves to detecting the prefix signal P again. If it has not been completed, the processor subtracts m by one, returns to process 1, and moves on to displaying the next test pattern. In this way, the signal sending side does not have to change the test pattern and send it many times, but can perform a test by using a specific pattern for the frame synchronization signal and sending it once.

In addition, other methods for setting the test state include using a call signal and changing the state of the input port of the decoder with a switch.

[Explanation of effects]

As explained above, according to the present invention, display tests are stored in advance and automatically executed according to display patterns. The test is simplified and can be performed accurately.

FIG. 1 is a block diagram of main parts of an embodiment of the present invention.

FIG. 2 is a detailed diagram of the decoder.

FIG. 5 is a diagram showing the format of a received signal.

Figure 4 is a flowchart of the display test.

FIG. 5 is a diagram showing a test pattern.

DESCRIPTION OF SYMBOLS 1... Antenna, 2... Radio part, 3... Waveform shaping circuit, 4... Decoder, 5-P-ROM, 6
-...Amplifier, 7...Speaker, 8...L(!D1
10... Program counter, 11-- Control unit, 12
・-・Prog sim counter, 13-data bus.

Patent applicant NEC Corporation.

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Claims (1)

[Claims] (1) A radio unit that demodulates a received signal, a decoder that decodes a local calling number and display information from a post-tuning signal from the radio unit, and means for emitting a beeping sound based on the output of the decoder; In a wireless selective discharge receiver equipped with a display means for visually displaying p display information based on the output of the decoder,
The decoder includes a control unit including a microprocessor, and when a display test pattern is detected from the signal received by the wireless unit, the control unit automatically displays the test display pattern on the display means according to a programmed procedure. - A wireless selective calling receiver configured to display sequentially.