JPS58129669A - Two-chip microcomputer - Google Patents

Abstract

PURPOSE:To enable enlargement of the system and to give flexibility by having the function of a microcomputer into program controlling system circuit chips. CONSTITUTION:A data processing chip 2, a program counter 11 in a program controlling chip 1 and other registers are set to initial condition by initial set signals. Between these chips 1, 2, data processing instruction is sent from a controlling chip 1 to processing chip 2, and program controlling information such as condition code, interruption information etc. is sent out from the processing chip 2 to controlling chip 1 through a data line DL. Controlling signals for controlling request of data, sending of data, giving and receiving of data are transmitted between chips 1, 2 through controlling lines CL provided one for each correspondingly.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a micro-combination consisting of two parts, two parts, and one part.

[Technical background of the invention and its problems]

The integrated circuits that make up the microcombi, -Y, are the single-chip microcombi, -Y, and N1 model large T! for small Ml controllers. Multi-chip microderosenafte structures are often used for system configurations.
However, the above single-chip microcombi, -
However, a multi-microprocessor system has the disadvantage that the system is small and lacks flexibility, and a multi-microprocessor has a large number of lines between chips, and therefore a large number of bins, resulting in a large O influence between chips.

[Purpose of the invention]

The present invention was developed to eliminate the disadvantages of a single-chip microcomputer; it can expand the system (program area) and provide flexibility, while reducing the number of lines between chips. can reduce the number of pins and reduce the influence between chips2
The aim is to provide a chip micro combination.

[Summary of the invention]

In order to achieve the purpose of the Royal Palace, according to the present invention, the functions of the main unit are divided into two, and one side is divided into two parts: arithmetic logic circuits, registers, RAM, Ilo (input/output) 11!
The data processing chip includes an interrupt priority control circuit and a data processing instruction decoding circuit, and the other is a 10-gram ROM.
, program counter.

Including program stack and branch instruction decoding circuit! The data processing commands (control chip → processing chips, chips) and program opening information (control chips, chips, chips, and interrupt information) are connected between these two chips and chips.
→ control chip).

[Embodiments of the invention]

Hereinafter, before explaining one embodiment of the present invention in detail with reference to the drawings, the general outline of the present invention will be explained.
- The instructions in the evening program are broadly divided into data processing instructions and program 7a - [- control branch thread instructions. The latter instruction usually has an address part, and its size determines the address space of the program.

If the number of bits in the address part is very large, it is possible to perform a large number of 4 DRAMs, but since the number of bits per instruction is large, the memory efficiency is poor. If the number of bits of the address is small, the number of bits of the instruction is small, but l[Ia
The capacity of the self-printing machine becomes smaller.

Changing the number of bits or instructions is changing the instruction set), which may lead to the creation of a Mital combination. However, with respect to the data MilK, branch instructions make no contribution in terms of I[Ii, and are unrelated to the bit length of branch instructions. Therefore, if we separate the data processing circuit and the program control circuit, the difference in the bit length of the address part of the branch instruction will only affect the latter.The data processing circuit will receive the data processing instruction and process it. Just run it, the size of the program, ie! It has nothing to do with the size of rodaram memory. Also,
Branch instructions are irrelevant with respect to data processing. Therefore, when the data processing circuit and the program control circuit are separated, the information exchanged between these two circuits is as follows. A data processing command is given to the data processing circuit from the program control circuit. Ninth, the flow of the program is controlled based on the data processing results, and the data processing circuit sends a condition code and an interrupt request code! Send to Rodala 5 control system circuit. Address information for program branch rounding is ineffective in data processing.

In Figure 1, two circuits as described above are constructed with separate chips, respectively, and 92 circuits are formed! This shows the specific circuit of the microcombi. J is! Rodara five control chip〉
, 2 is a data processing chip. The data ram control circuit 1 and del 1 are decoded into a ROM (read only memory) 3% which stores instructions, an instruction register 4 which stores instructions from this ROM 3, and a branch instruction from this instruction register 4. The branch instruction decoder 5 and the instruction register 4 send out the control signal as a control signal (07 rV)1. f”-
Execution address decoder C for storing data, driver r1 for sending data processing instructions to data processing step 1 side
Processes the data processing, code, and interrupt information, which will be described later.

Code analysis II for decoding the register 4# received from the CPU 1 side, the condition code and interrupt code from this register/41 and the branch instruction code I! Side road 9, ζO
In circuit 0 output determines cabinet address - branch address, return address.

A selector IQ for selecting one of the sequential addresses, a program counter 1 for addressing the ROM 3 based on the address selected by the director 1o, and a +1 circuit for incrementing the contents of the program counter 11. 12. A pushbutton that stores and retains the address information when necessary (at the time of an interrupt or subroutine branch);
Downstar, Ri13. It has a transfer control circuit 14 and the like that exchanges transfer control information with the data processing chip 2.

First, the data processing chip 1 has a dry buffer 5. which transmits and receives data to and from the program control chip 1. Resino arm 16. An instruction register for storing instructions received by the resino paddle 16; a right register j Os for storing the numerical values from these left and right registers x9m2o; Resino 41 - Address register 2 that stores addresses sent from other circuits
1. A RAM (Random Access Memory) 14 that writes data to the address specified by this address register 11. A register xi that stores data read from this RAM J4, and an external I10 device. I10 register z6 for storing private data sent and received by
A condition code register 11 that stores a condition code, an interrupt priority control circuit 28 that controls interrupt priority according to an external interrupt request signal and the condition code, and a transfer control circuit 2 similar to the above-mentioned one. The data processing chip 2, the program counter 11 in the program control chip f1, and other registers are set to an initial state by an initial reset signal. Between these chips 1.1, data processing instructions are transferred from the control chip 1 to the processing H4fdde1.
Ofm duram control information such as output and m-input information is sent from the processing chip 2 to the control chip f1 via the data 〇L of tf8ry), data aS request, data transmission, f
- One control signal for controlling transmission and reception in the evening is provided for each signal, and is transmitted between the te and the d 1 #2 via the 9 control@CL.

An example of data transfer control timing between chips 2 and 11.2 is shown in FIG. 2. However, this example shows a case where the data processing chip 1 side has the initiative. Now, in the initial state, the control circuit 2# from chip 2 to chip 1
When the data request signal of becomes high level 1H1 at time kl, in step 1, the data request signal of time 1. A data processing command is sent from chip 1 to chip 2 via data@DL at time 1.
．． The control circuit 14 sends transmission control information from the chip 1 to the chip 2 through the control line CL. As a result, the chip 2 that received the data processing command receives the data processing command at the reception completion time t4.
, the data request signal is set to low level °L'', and from this K, chip I starts control 1 in the control circuit 34 at time t-.
The data transmission/reception of 1cL is interrupted, and the transmission of data processing commands of data 11DL is stopped. Next, at time t, when log 2 control information such as condition code 1 interrupt information is sent from the data processing step 1 to the log module control unit Jll via data@DL, the control circuit 2 #
The data transmission on the control line CL becomes in progress at time tvK. Above with 1 chip! When the rodaram control information is received, the reception is completed at the data transmission/reception company time t@ on the control line CL in the control circuit 14. With the completion of this 0111 communication, the r-voice transmission on the data line DL by chip 1 is started at time t.
・At the same time, the control line CL is connected to the control circuit 1#.
The completion of data transmission and reception on the control line CL in the chip 10 control circuit 14 is reset at time 1 by the disconnection of the line during transmission of the fist ζO that interrupts the data transmission to the chip 10. In this way, Data and control information are exchanged between both chips and fx ax, and the data sum is processed based on these O data and control information. When expanding the wing QM J ), the address part of the branch instruction will be changed.

For example, as shown in Figure @3, you can expand the number of bits in the address field, or you can expand the execution address by using the sedamentation method. These things do not affect data processing instructions. do not have.

Among the data processing instructions provided to the data processing chip is an address portion of the data memory (RAM J 4 and I10 register 26). Therefore, in order to expand these address spaces, the data processing system circuitry must be changed by changing the data processing system instructions.

However, the change does not affect the program control system circuit. However, the contents of ROM J in which the program is stored will naturally change. Various methods can be considered for expanding the data memory, but the method is basically the same as the method for expanding the program memory. That is, data memory (RAM
J 4 and! Of course, even when using a small-capacity circuit within the address space limitations of the 10 registers 26) and the program memory (ROM I ), the memory capacities of both circuits can be determined independently of each other.

ζThe above-mentioned nine-string command refers to the following command.

Namely, they are unconditional jump, conditional fraction 1 fjt, ty routine call, suit arm part call, subroutine return 1 interrupt return, and trub group.

According to the above-mentioned chip mital computer, processing chip,
The size of f2 and control chip 1 can be determined or selected independently, and they do not affect each other, making it easy to expand the system. In particular, processing te and de 2 are completely dependent on program thickness 1. It can be used commonly. Furthermore, the number of wires between the processing chip 1 and the control chip 1 is extremely small (for example, 8 data lines DL, 8 control lines DL,
3 for a total of 11), control chip, and 7" JO terminals are very few (for example, 1 including the above 11 wiring and power supply terminals)
4 bottles). In addition, if data transmission between both chips is performed bit serially, the number of wires will increase further.

The number of bins can be reduced.

Further, according to the present invention, it is possible to easily configure a system of J)mXm building with n+n+ chips including n types of processing chips f2 and m types of control chips.

〔Effect of the invention〕

As explained above, according to the present invention, by dividing the functions of the microcomputer body into two, the program control system circuit chip and the data processing system circuit chip, the system can be expanded significantly compared to a single-chip combination. 2-chi, de-microcomputers, which can be easily made flexible, reduce the number of lines between both chips and f, reduce the number of wires, and reduce the influence between chips. -Can provide evening meals.

[Brief explanation of the drawing]

1!41 is a configuration diagram of a 2-chi, microcombi, and evening system according to an embodiment of the present invention, FIG. 2 is a time chart for explaining the operation of FIG. 1, and FIG. 3 is a diagram of FIG. 1. 1... Program control chip, 2... Data processing chip, 3... ROM, 4... Instruction register, 5...
・Minute m instruction decoder 16...execution address decoder,
1.15... Dry/Do, Il, 1M... Receiver, -... Code decoding circuit, 10... Selector, 11
...De-four-gram counter, 11...+1 circuit, IJ
...de, shi, 〆unsta, ri, 14. :II...Transfer control circuit, JF-・instruction register, 18...decoder, 1#・go, xs...register, 21...arithmetic circuit, 21...aki, muleta, JJ-... Address register, j4... wing M, x-...! 10 register, 21...Condition, code register, 21...
・Interrupt priority control circuit・

Claims (3)

[Claims] (1) A data processing chip having a data processing circuit including an arithmetic logic circuit, a register, a RAM, an input/output port 1 interrupt priority control circuit, and a data processing instruction decoder, a program ROM, a program counter, a program star, The program system @1 has a program control system circuit including a branch instruction decoder, and data processing instructions and program control information are exchanged between the two chips through a link between the two chips. A two-chip micro combination, which is characterized by being designed to do the following: (2) Data processing from the program control chip! Data processing commands are sent to data processing commands. From the program 2 control chip to the code 1
2. The two-chip microcombiner according to claim 1, wherein the two-chip microcombiner transmits program control information including interrupt information. (3) The extension of the program ROM includes changing the address field of branch instructions to I#FgIl.