JPS58126086A - Mutual interference preventing circuit of plural robots - Google Patents
Mutual interference preventing circuit of plural robotsInfo
- Publication number
- JPS58126086A JPS58126086A JP104182A JP104182A JPS58126086A JP S58126086 A JPS58126086 A JP S58126086A JP 104182 A JP104182 A JP 104182A JP 104182 A JP104182 A JP 104182A JP S58126086 A JPS58126086 A JP S58126086A
- Authority
- JP
- Japan
- Prior art keywords
- interference
- signal
- memory
- area
- input
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
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- Numerical Control (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
本発−は、ｍ数台Ｏｐｌットを同時に作動させるものに
おいて、１７）０ロゼツトＯｆ１１１１Ｉ１ｍ１１ｍが
＠０四−ットの作動範囲と一部重徹す為場合γ
における相互干渉防止１１１Ｈｃ関する。DETAILED DESCRIPTION OF THE INVENTION The present invention is designed to operate several Oplots at the same time, and in the case of Regarding mutual interference prevention 111Hc.
従来、この−〇干渉の防止Ｏえめに、ロゼツトの作動重
厚に予め優先順位上押たせて行うもＯがあるが、優先順
位を決める作１１が繁雑でＴｏｊ。Conventionally, in order to prevent this -〇 interference, it has been possible to prioritize the operation of the rosette in advance, but the step 11 of determining the priority is complicated and too complicated.
また優先拳位の高いｗ／フット例えばＳ接棒の霞着、ア
ークが発生しない等Ｏ故障によ）遥れて作−すゐと、低
馳位Ｏ−Ｉットは待機する友め、いたずらに時間を空費
し作業能率が暴くなる欠点かＴｏ為、まえ、田ｌットに
その作動を教示する段階で各ａｄフット互に干渉し表い
ようにその作動重厚を考慮するものもあゐが、 ａｄフ
ット多数ある場合、ポイン）１１０作−スピード、飼え
ばＳ＊スピードが異なる等Ｏえめ１ロゼツト間に干渉が
ないようにＷｄｉ！ットに教示を与えることは崗−であ
）、壜え口Ｉットが作−途中で故障した場合には、干渉
検出装置によｐロボットが停止し１作動させるには手動
操作に戻し、オペレータが互いの干渉を避けるようにロ
ボット會−尋させなけれけならない欠点がある。In addition, if the w/foot has a high priority position (e.g., the S connection rod is smeared, the arc does not occur, etc.), the work is far away, and the low position O-It is a friend who is on standby. The drawback is that it wastes time unnecessarily and the work efficiency is exposed. Therefore, when teaching the robot how to operate, there are some that take into consideration the seriousness of the operation, as shown by the fact that each AD foot interferes with each other. If there are a lot of ad feet, please note) 110 works - speed, S * speed will be different if kept, etc. Wdi so that there is no interference between 1 rosette! (It is difficult to give instructions to the robot), but if the bottle spout breaks down during production, the interference detection device will stop the robot and the robot will have to return to manual operation to operate. However, there is a drawback that the operators must be able to interact with the robots to avoid mutual interference.
本発明Ｆｉ、複歓のロゼツトのうち最初に干渉領域に進
入する４（７０作−を優先させ、その他のものの作動【
最初のものが干渉領域から脱崩するまで待機させるよう
にして、前記し九贅来のものの欠点管無くするもので、
＊＊台Ｏ口Ｉットか同時に作動するものにおいて、諌
各口ｌットは記憶−Ｉｔ有し、陳記憶Ｉ踏には、予め教
示された他Ｏ口ｌットとＯ干渉領域良びその墓前に発生
する干渉信号が入力するようにし、前記干渉領域に最初
に進入するＷ＆ツ）０記憶−隆＃ｉｓ前記干＃ＩＩＩ号
により作−して、鋏會号が入力している間持続する干渉
告知ｇＭ号を出力し。In the present invention, among the multiple rosettes, priority is given to 4 (70 pieces) that enters the interference area first, and the operation of the others [
This eliminates the drawbacks of the nine previous ones by making it wait until the first one collapses from the interference area.
**In the case where both the stand and the head operate at the same time, each head has a memory, and the memory has a pre-taught area of interference with other heads. The interference signal generated in front of the grave is input, and the W&T that first enters the interference area is created by the above-mentioned No. Outputs continuous interference notification gM.
その＠ＶＯＷットの配憶−路は、最初のロゼツトから出
力し友前記干渉告知伽号によりリセット動作して、ｌ［
信号か入力している間持続すみ干渉領域への進入禁止準
備信号を出力し、ｇ＊その他の−ｌフット、該進入禁止
準備信号とそＯ後入力する干渉信号とにより、前記干渉
領域への進入が阻止されること１ｗ像とする。The storage path of @VOW is output from the first rosette and is reset by the interference notification signal.
While the signal is being input, an entry prohibition preparation signal to the interference area is output, and the entry prohibition preparation signal and the subsequently input interference signal are used to prevent entry into the interference area The 1w image is that the entry is blocked.
以下本発明Ｏ実施例を因面にり龜説明する。Embodiments of the present invention will be explained in detail below.
第） ｍｉｊ ＠ ｗ ＃ ｙト１ｂＸ！個Ｏ場会の各
Ｅｌ＆ｆｆ）０作−範一における干渉領域ＯＩ！明閣で
ある。Chapter) mij @ w #yto1bX! Each El & ff) 0 work-interference area OI in Hanichi! It is Ming Pavilion.
鳳、ｂはそれぞれ口ｌツ） Ｉ Ｉ ］［０作−作動軌
跡で１点ｌからＡ９及び点ｌから点１１は、４）四ポッ
トの作一時の軌跡を教示するステップ数である＊ ４）
’ ｚットＩ、■ＩＣ）８作−範−ｃ、ｓｌは図示の
通りであるから１口Ｉツ）Ｉでは、ステップＳ〜７迄Ｏ
関が干渉領域であフ１ロＩット厘ではステップ３〜！Ｓ
迄Ｏ関が干渉領域である。0 production - A9 from point 1 and point 1 from point 1 in the operation trajectory are the number of steps to teach the trajectory during production of 4) four pots * 4 )
' zt I, ■ IC) 8 pieces - range - c, sl are as shown in the diagram, so in 1 bite I tsu) I, from steps S to 7 O
If the barrier is in the interference area, step 3~! S
The area up to O is the interference area.
第２園は本発−Ｏ実施例■賂で、１．１はそれぞれ口ｌ
ツ）１．１の制御ＩＩＩＩを示し、これ等は岡じ構成で
あり、信号−（１）で相互に接続されている。 （２
Ｋ） （２ｍ社１例えばＲ−８７リツプフロツゾからな
る記憶回路、、 （１１）（３自）ｔｊＮＡＮＤ回路、
−（４ｓ ）（４愈）ＦｉＮＯ？ａ１ｗｈ−（！！ｓＸ
５ｍ）＊ ’） Ｖ −。The second garden is the main origin - O example ■ bribe, 1.1 is each mouth l
T) Control III of 1.1 is shown, and these have the same configuration and are interconnected by signal -(1). (2
K) (2m company 1, for example, a memory circuit consisting of an R-87 lip flop, (11) (3) tj NAND circuit,
-(4s) (4愈)FiNO? a1wh-(!!sX
5m)*')V-.
（６１）（６雪）ＦｉＡＮＤ回路ｅ（７ｔＸ７ｍｌはＮ
ＯＴ回路である。(61) (6 snow) FiAND circuit e (7tX7ml is N
It is an OT circuit.
記憶回路（２ｓ Ｘ ２ｍ ）のセット端子Ｓには１ロ
ゼツトＯ作動前に予め教示されてメモリ勢に記憶され、
干渉領域にロゼツトの作動か進入する墓前及び該領域中
にｍ出される干渉信号が加わるようにする。The set terminal S of the memory circuit (2s x 2m) is taught in advance before 1 rosette O is activated and is stored in the memory.
The interference signal is added to the interference area in front of the grave into which the rosette is activated and which is emitted into the area.
ＮＡＮＤｉｉｌｊｌ （３ｔＸ ３ｓ）ｔｌ、そ１２）
１入力端子に干渉信号か、他の入力端子１リレー（５１
０Ｓ）Ｏ８点（５ｓａ ） （５ｉａ ） （’ ＷＡ
成により生ずる干渉告知信号がそれぞれ入力するように
する。ＡＮＤ回路（６Ｉ）（６ｓ）は、第１入力端子が
記憶回路（２ｓ Ｍ ２ｍ）の出力亀子に、第２入力端
子がＮＯ’ｆｌｌｌ路（７ｔＸ７ｍ）を介して信号−（
１） Ｋ％無３人力鴫子が記憶ａｍ（２＊）（２ｍ）の
セット端子８にそれぞれ接続され。NANDiiljl (3tX 3s)tl, part 12)
1 input terminal has an interference signal, or other input terminal 1 relay (51
0S) O8 points (5sa) (5ia) (' WA
The interference notification signal generated by the configuration is inputted respectively. The AND circuit (6I) (6s) has a first input terminal connected to the output terminal of the memory circuit (2s M 2m), and a second input terminal connected to the signal -(
1) K%less 3 man-powered machines are connected to the set terminals 8 of the memory am(2*)(2m), respectively.
後から干渉領域に進入しようとするａｄットＯ餉ｌｌｌ
１励賂では歩道禁止信号を出力する。An ad that attempts to enter the interference area from behind
For 1 reward, a sidewalk prohibition signal is output.
今、鶏１図示のように例えばロボツ）Ｉかステップ３′
＊で作−して干渉領域に進入しようとし。Now, as shown in the diagram, chicken 1 (for example, robot) I or step 3'
* and try to enter the interference area.
ロゼツトｌはＷ領域よｐ＊れ九位置にあゐとすると、Ｏ
ｆツ）ｌの干渉信号はメモリ等から貌み出されて記憶回
路（２ｍ）に入力し、その出力である干渉告知信号によ
ｊｖシレー５鵞）は作−してそＯＩｔ Ａ （５ｓａ
） を閉成する。かくて、信号−（１）には干渉告知信
号が発生し、４）制御１１１１１．１４Ｄ ＮＡＮＤｌ
ｉｌｊｌ （３ｔＸ ３ｓ）Ｋ加わる。Assuming that the rosette l is at position p*9 from the W area, then O
The interference signal of ftsu)l is extracted from the memory etc. and input to the storage circuit (2m), and the output of the interference notification signal is used to generate the
) is closed. Thus, an interference notification signal is generated in signal-(1), and 4) control 11111.14D NANDl
iljl (3tX 3s)K is added.
配憶ＩＣ１ＩＩ（２婁）は干渉信号が入力しているＯｆ
。Memory IC1II (2 婁) is of which the interference signal is input.
.
ＮＡＮ、Ｄｌｌ路（３３）から、ｖセット端子Ｂ Ｋ
Ｖ −ｋ ７ト信号か加わっても鋏記憶−路（２嘗）は
依然として干渉告知信号を出力する。一方、−ｌツ）１
は干渉信号がまだセット端子８に加わらないので、リセ
ット信号によ）記憶−路（２１社リセットされゐ、そこ
で、 ｇ＋＋ｓｓ路（２１）から干渉領域への進入禁止
準備信号が出力してＡＮＤ回路（Ｉｔ ）Ｋ加わ９．鋏
−路會進入禁止準備状簡にする。し九がって口ｌツ）Ｉ
が墓に続いて干渉領域に進入しようとして発生した干渉
信号１１１Ｅｌ［ＡＮＤ−踏（６１）に加わると％＠０
２入力端子には進入禁止準備信号及び干渉告知信号か入
力している丸め１ＩＷｉＡ絡（６重）は歩道禁止信号管
出力し、皺會号によりロゼツ）Ｉｔ！干渉領域に進入す
るのｔｍ止される。From NAN, Dll path (33), v set terminal BK
Even if the V-k7 signal is applied, the scissors memory path (2nd generation) still outputs the interference notification signal. On the other hand, -ltsu)1
Since the interference signal has not yet been applied to the set terminal 8, the memory path (21) is reset by the reset signal, and a preparation signal for prohibiting entry into the interference area is output from the g++ss path (21) and the AND circuit is activated. (It) K joins 9. Scissors - Write a preliminary letter prohibiting entry to the road meeting.
Interfering signal 111El [AND-tread (61) generated when attempting to enter the interference area following the grave is %@0
The round 1 IWiA circuit (six layers) which inputs the entry prohibition preparation signal and interference notification signal to the 2 input terminal outputs the pedestrian prohibition signal tube, and the wrinkled signal is output) It! Entry into the interference area is prohibited.
ａｓｔｙ）ｌか最初に干渉領域に進入する場合について
もこれと岡じ動作ｔ−Ｌ、 ロボット鳳Ｆｉロボッ）Ｉ
か干渉領域にある間その進入が阻止される。Asty)l also performs the same operation when entering the interference area for the first time.
or its entry is blocked while it is in the interference area.
リポＶ実施例では２１ｉ１４りロボットの制御回路が示
されるが、多数儒の場合には制御■路ｌ、鳳と、岡橡Ｏ
回路會増設し信号＄１（１）で接続すれとよい。In the example of LipoV, the control circuit of the 21i14 robot is shown, but in the case of majority control, the control circuit is
It would be better to add a circuit and connect it with the signal $1 (1).
このように本発明によれば、予め教示され九他の口Ｉッ
トとの干渉領域及びそのｉｌｌ！ＩＩＫ尭生する干渉信
号が入力する記憶回＃６を各口ｌツシは有し、前記干渉
領域に最初に進入するＷ／ットＯ配配憶絡路、前記干渉
信号により作動して鋏會号が入力している間持絖する干
渉告知信号を出力し、その伽Ｏ口ｌットの記憶回路は、
最初のロゼツトから出力し喪前記干渉告知信号によりリ
セット輪作して鋏傷号が入力している関持絖する干渉領
域への進入禁止準備信号を出力し。As described above, according to the present invention, the area of interference with nine other mouths and its ill! is taught in advance! Each mouthpiece has a memory circuit #6 into which the interference signal generated by IIK is input, and the W/O distribution circuit that first enters the interference area is activated by the interference signal and the scissor meeting is performed. It outputs an interference notification signal that remains while the signal is being input, and its memory circuit is
The first rosette outputs a reset signal based on the interference notification signal, and outputs a preparation signal for prohibiting entry into the interfering area where the scissors signal is input.
腋その伽Ｏａ ｄット扛、陳進入禁止単備傷号とそのＩ
ｋ大入力大干渉信号とにより前記干渉領域への進入が阻
止されることを４Ｉ像とし、複数Ｏ口ｌツ）０５％最初
に干渉領域に進入する４０の作動ｔｉｌ先させ、そａ４
１Ｉｏ％００卿−を最初のものが干渉領域から脱めす為
まで待機させるようにしたので１作動前におけゐ口ｌッ
トに対する作動の教示が、干渉領域を考慮しなくてよい
ため容易であると共に、作東時ＩＭＩＩＫ無駄がなく作
業能率か向上する勢の効果を有する。Armpits Oa dt 扛, Chen's entry prohibited single beiju issue and its I
It is assumed that the entry into the interference region is blocked by a large input large interference signal.
Since the 1Io%00 sir- is made to wait until the first one leaves the interference area, it is easy to teach the operation to the mouth before the first operation because there is no need to consider the interference area. At the same time, it has the effect of eliminating waste and improving work efficiency during production.
ｔ ｌｌＮｌ０簡単１に説明
第ｉｌｌは％ＩＮ数台Ｏ酵ｌツ）０作動範■における干
渉領域Ｏ１！ＷＡ図、馬２図は本発−の一実施例のｇｓ
ｍｍである。tllNl0Easy explanation 1st ill is %IN several units O fermentation ltsu) 0 interference area O1 in the operating range ■! WA diagram and horse 2 diagram are gs of one example of this invention.
It is mm.
１．１・・・■ｌフットびそＯ制御胞路。1.1...■lFootbisoO-controlled tract.
（１ト・・信号線−（２１Ｍ ２ｍ ） ・・・記憶−
路。(1t...Signal line-(21M 2m)...Memory-
Road.
（３＞）（ｈ）・・・ＮＡＮＤ回路。(3>) (h)...NAND circuit.
（Ｓｓ Ｋ Ｓｍ ） ・・’リレー。(Ss K Sm)...'Relay.
（６１）（６ｇ）・・・歩道禁止信号出力用ＮＡＮＤＱ
ＩＩ。(61) (6g)... NANDQ for outputting pedestrian prohibition signal
II.
Claims (1)
各ａｄットは記憶ＩＩＩを有し、ＩＩ記憶１ｃｉｓＫＦ
ｉ、予め教示１れ九他０口Ｉットとの干渉領域及びそＯ
直前に発生する干渉信号が入力すみようにし、前記干渉
領域に最初に進入する口ｌツ）０記憶−路は、前記干渉
信号により作動じて、咳信号が入力している間持絖する
干渉告知傷号會出力し、その伽のｗ／ツ）０記憶−路は
、最初のロゼツトから出力し良前記干渉告知修号によタ
リセット動作して、［信号が入力している関持絖する干
渉領域への進入禁止準備信号を出力しＳ１１［その伽の
ロボットは、骸進入ｉｌｌ止準備信号とその後入力する
干渉信号とにより、前記干渉領域への進入か阻止されゐ
こと會彎黴とする＊＊台Ｏ−ボッ）Ｏ相互干渉防止回路
。In the case where 11 ad units are operated simultaneously, each ad unit has memory III, and II memory 1 cisKF.
i. Pre-taught areas of interference with other parts and their
The interference signal generated just before is input, and the first memory path that enters the interference area is activated by the interference signal to prevent interference that lasts while the cough signal is input. Output the interference notification signal, and output the 0 memory path from the first rosette. A preparation signal for prohibiting entry into the interference area is outputted, and S11 [The robot in question is prevented from entering the interference area due to the preparation signal for preventing entry into the skeleton and the interference signal input thereafter. **Unit O-Bot)O Mutual interference prevention circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP104182A JPS58126086A (en) | 1982-01-08 | 1982-01-08 | Mutual interference preventing circuit of plural robots |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP104182A JPS58126086A (en) | 1982-01-08 | 1982-01-08 | Mutual interference preventing circuit of plural robots |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS58126086A true JPS58126086A (en) | 1983-07-27 |
| JPH0254565B2 JPH0254565B2 (en) | 1990-11-22 |
Family
ID=11490470
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP104182A Granted JPS58126086A (en) | 1982-01-08 | 1982-01-08 | Mutual interference preventing circuit of plural robots |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58126086A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5339446A (en) * | 1986-12-26 | 1994-08-16 | Kabushiki Kaisha Toshiba | Power supply and method for use in a computer system to confirm a save operation of the computer system and to stop a supply of power to the computer system after confirmation |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5321056A (en) * | 1976-08-10 | 1978-02-27 | Shin Meiwa Ind Co Ltd | Method of controlling position controller |
| JPS5378556A (en) * | 1976-12-23 | 1978-07-12 | Toshiba Corp | Control device |
-
1982
- 1982-01-08 JP JP104182A patent/JPS58126086A/en active Granted
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5321056A (en) * | 1976-08-10 | 1978-02-27 | Shin Meiwa Ind Co Ltd | Method of controlling position controller |
| JPS5378556A (en) * | 1976-12-23 | 1978-07-12 | Toshiba Corp | Control device |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5339446A (en) * | 1986-12-26 | 1994-08-16 | Kabushiki Kaisha Toshiba | Power supply and method for use in a computer system to confirm a save operation of the computer system and to stop a supply of power to the computer system after confirmation |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0254565B2 (en) | 1990-11-22 |
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