JPS58112348A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS58112348A
JPS58112348A JP56211715A JP21171581A JPS58112348A JP S58112348 A JPS58112348 A JP S58112348A JP 56211715 A JP56211715 A JP 56211715A JP 21171581 A JP21171581 A JP 21171581A JP S58112348 A JPS58112348 A JP S58112348A
Authority
JP
Japan
Prior art keywords
chip
external conductive
semiconductor
terminal
conductive terminal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP56211715A
Other languages
Japanese (ja)
Other versions
JPH0445981B2 (en
Inventor
Nobuhiko Mizuo
水尾　允彦
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP56211715A priority Critical patent/JPS58112348A/en
Publication of JPS58112348A publication Critical patent/JPS58112348A/en
Publication of JPH0445981B2 publication Critical patent/JPH0445981B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L25/105—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1017—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support
    • H01L2225/1023—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support the support being an insulating substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1047—Details of electrical connections between containers
    • H01L2225/1058—Bump or bump-like electrical connections, e.g. balls, pillars, posts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1047—Details of electrical connections between containers
    • H01L2225/1064—Electrical connections provided on a side surface of one or more of the containers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/15165—Monolayer substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16195—Flat cap [not enclosing an internal cavity]
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/3447—Lead-in-hole components

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE:To obtain a chip carrier mounted semiconductor device having a structure that the device can be loaded vertically to a wiring substrate. CONSTITUTION:In a structure wherein the mount density is most enhanced, semiconductor memory devices 35 are erected and arranged on the wiring substrate in a state that each is contacted on the upper and lower surfaces, and the pin external conductive terminal 21 of each semiconductor memory device 35 is inserted into a fixed through hole 37 in the wiring substrate 36, then soldered and fixed. On a coat external conductive terminal 22 the common signal terminal in each memory device 35, a series of common signal wires constituted respectively of conductor 39 are soldered at every row. Two pieces of the pin external conductive terminal are provided, but any number of pieces are available as required. Or, one, which is bar form and formed by burying one end in the carrier, can be also used. While, the cap can be formed of ceramics. Further, it is applicable to a metallic package and a plastic package.

Description

【発明の詳細な説明】 く耐　発明の技術分野 本発明は半導体チップがチップ・キャリアに実装された
半導体装置に係り、特ｉこ半導体チップとして半導体メ
モリ素子がチップ番キャリアに実装された半導体装置に
於ける外部導電端子の構造に関する。[Detailed Description of the Invention] Technical Field of the Invention The present invention relates to a semiconductor device in which a semiconductor chip is mounted on a chip carrier, and particularly relates to a semiconductor device in which a semiconductor memory element is mounted as a semiconductor chip in a chip carrier. This invention relates to the structure of external conductive terminals in

伽）　技術の背景 計算機システム等の大規模化に伴い、該計算機システム
に搭載される半導体メモリ素子等の半導体集積回路（Ｉ
Ｃ）素子の数は非常に膨大となってきており、このこと
はシステムの大型化を招き、それに伴ってシステム内の
配置７１！ｋｙり１！ｋ＜なり計算速度の低下を招く、
そこで、計算機システム等に対する半導体ＩＣ素子の実
装密度を高めシステムの大型化を抑える手段として提供
されたのが、チップ・キャリア実装構造の半導体ＩＣ装
置である。伽）Technical background With the increase in the scale of computer systems, semiconductor integrated circuits (I) such as semiconductor memory elements installed in these computer systems
C) The number of elements has become extremely large, which leads to an increase in the size of the system and, accordingly, the arrangement within the system 71! Kyri1! k<, which leads to a decrease in calculation speed,
Therefore, a semiconductor IC device with a chip carrier mounting structure has been provided as a means of increasing the packaging density of semiconductor IC elements in a computer system and the like and suppressing the increase in size of the system.

（ｅ）　　従来技術と問題点 従来から用いられているチップ・キャリアの中で、最も
実装密度が高められる構造にリードレス・チップ・キャ
リアがある。第１図はリードレス・チップ・キャリアに
実装された半導体ＩＣ装置に於ける一例の断面図（イ）
及び底面図（口〕を示したものである。そして１図１こ
於てｌはセラ建ツク基板、２はセラミック枠、３は表面
に金（Ａｕ　）めっき等が施されたチップ・ステージ、
４は表出部に＾Ｕめっき等が施されている内部配線、５
ヰ内部配線からそれぞれ延出されＡｕめっき等が施され
ている外部配線、６は外部配線がそれぞれ底面に延出さ
れ表面にＡｕめっき等が施された被験状の外部端子、７
はキャップろう付は用メタライズ層、８は金属キャップ
、９は銀（Ａｇ）合金等のろう材、１０Ｆ１半導体ＩＣ
チップ、１１はボンディング・バッド、１２ｄアル＜＝
ラム（Ａｔ）等のボンディング・ワイヤ、１３は金（Ａ
ｕ）／シリコン（Ｓｌ）層を示している・ このような構造を有する従来のチップ舎キャリアに実装
された半導体ＩＣ装置は、計算機システム等に配設され
る配線基板に対して底面を下にして水平に（平面）実装
される。その実値状態を示したのが第２ＷＪで、図中１
４は前記チップψキャリア実装構造の半導体ＩＣＣ重置
１５はセラミクス成るいはプラスチフスにより形成され
た配線基板、１６Ｆｓ配線パターン、６は前記外部端子
、１７は半田等のろう材を表わしている。(e) Prior Art and Problems Among conventionally used chip carriers, the leadless chip carrier has a structure that allows the highest packaging density. Figure 1 is a cross-sectional view (A) of an example of a semiconductor IC device mounted on a leadless chip carrier.
and a bottom view (opening). In Fig. 1, l is a ceramic building board, 2 is a ceramic frame, 3 is a chip stage whose surface is plated with gold (Au), etc.
4 is internal wiring whose exposed part is coated with ^U plating, etc., 5
ヰExternal wiring extended from the internal wiring and subjected to Au plating, etc.; 6, external terminals of the test form, each of which external wiring extended to the bottom surface and Au plating, etc. applied to the surface; 7;
1 is a metallized layer for cap brazing, 8 is a metal cap, 9 is a brazing material such as silver (Ag) alloy, 10F1 semiconductor IC
Chip, 11 is bonding pad, 12d al<=
Bonding wire such as ram (At), 13 is gold (A
u)/Silicon (Sl) layer is shown. Semiconductor IC devices mounted on conventional chip carriers with such a structure are placed with their bottom side down relative to a wiring board installed in a computer system, etc. Mounted horizontally (flat). The second WJ shows the actual value state, 1 in the figure.
Reference numeral 4 represents the semiconductor ICC superimposed structure of the chip ψ carrier mounting structure, 15 represents a wiring board made of ceramics or plastics, a 16Fs wiring pattern, 6 represents the external terminal, and 17 represents a brazing material such as solder.

上記のように従来のチップ・キャリア実装構造の半導体
ＩＣ装置に於ては配線基板に対して平面実装がなされる
ためｉこ、チップ−キャリアの平面積ｌこ工って実装密
度が制限され更に実装密度を高めることができなかった
。As mentioned above, in a semiconductor IC device with a conventional chip/carrier mounting structure, the mounting density is limited due to the planar area of the chip/carrier because it is mounted on a wiring board on a plane. It was not possible to increase the packaging density.

（ｄ）　　発明の目的 本発明は上記問題点に鑑み、配線基板に対して垂直に装
着することが可能°な構造を有するチップ・キャリア実
装の半導体装置を提供し、実装置ｒを向上せしめること
を目的とする。(d) Purpose of the Invention In view of the above-mentioned problems, the present invention provides a chip carrier mounted semiconductor device having a structure that allows it to be mounted perpendicularly to a wiring board, thereby improving the actual device. With the goal.

（ｅ）　　発明の構成 本発明は半導体装置に於て、半導体チップが、−外部側
面にピン状の導電端子を有し他の外部側面に被ｎ秋の導
電端子を有するチップ・キャリアに実装されてなること
を特徴とする。(e) Structure of the Invention The present invention provides a semiconductor device in which a semiconductor chip is mounted on a chip carrier having a pin-shaped conductive terminal on one external side and a second conductive terminal on the other external side. It is characterized by being

（ｆ）　　発明の実施例 以下本発明を、半導体メモリ装置に於ける一実施例につ
いて、第３図に示す上面図（イ）、ａ面図（ロ）。(f) Embodiment of the Invention The following is a top view (a) and an a-side view (b) shown in FIG. 3 of an embodiment of the present invention in a semiconductor memory device.

Ａ−Ａ　’矢視断面図ｅ１．下面図に）、及び第４図に
示す実装方法に於ける一実施例の上面図（イ）、１１面
図（ロ）を用いて詳細に説明する。A-A' cross-sectional view e1. A detailed explanation will be given using a bottom view (a), a top view (a), and an eleventh view (b) of an embodiment of the mounting method shown in FIG.

本発明を適用した半導体メモリ装置は、例えば９３図（
イ）、（ロ）、ｅ→、に）に示すよう、−側面に例えば
２〔本〕のビン状外部導電端子２１が配設され、他の三
側面に所望数の普膜状外部導Ｗ端子２２が配設されたセ
ラミック・チップ・キャリア２３内に半導体メモリ・チ
ップ２４が実装され％討チップ・キャリア２３上に例え
ば金属中ヤップ２５が封着されてなっている。なお前記
チップ舎キャリア２３に於けるピン状外部導電端子２１
は、通常構造の内部上９２６　ｍからチップ・キャリア
２３の一側面に延出された外部配置１２７ａ上に鉄／ニ
ッケル合金等通常の端子材料からなる例えばビン状打抜
き加工片が銀ろう２８等によりろう付けされて形成され
、又被膜状外部導電端子２２Ｆｉ内部配ａ１２６ｂから
チップ・キャリア２３の前記以外の三＠面に導出された
外部配置２７ｂ上に金めつき等が施されて形成される。For example, a semiconductor memory device to which the present invention is applied is shown in FIG.
As shown in a), (b), e→, and), for example, two bottle-shaped external conductive terminals 21 are arranged on the - side, and a desired number of membrane-shaped external conductive terminals 21 are arranged on the other three sides. A semiconductor memory chip 24 is mounted within a ceramic chip carrier 23 in which terminals 22 are arranged, and a metal core 25, for example, is sealed onto the chip carrier 23. Note that the pin-shaped external conductive terminal 21 in the chip carrier 23
For example, a bottle-shaped punched piece made of a common terminal material such as iron/nickel alloy is soldered with silver solder 28 or the like on an external arrangement 127a extending from 926 m above the inside of the normal structure to one side of the chip carrier 23. It is formed by brazing, and is formed by applying gold plating or the like on the external arrangement 27b led out from the internal arrangement a126b of the film-like external conductive terminal 22Fi to the other three @ sides of the chip carrier 23.

そして半導体メモリ・チップ２４は通常構造のチップ・
ステージ２９上に金／シリコン合金８０等を介してろう
付けされ、例えば該半導体メモリーチップ２４のチップ
・セレクト端子等チップ固有の信号が流されるパッド端
子３１ｍとピン状外部導電端子Ｉこ接続する内部配線２
６１とがアルミニウム等のボンディング・ワイヤ３１に
より接続される。又入出力端子、電源端子等容メモリー
チップに対して共通に配線されるパッド端子３１ｂと被
膜状外部導電端子２２に接続する内部上４１２６−ｂと
がボンディング・ワイヤ３２により接続される０本発明
の構造に於ては、通常このようξこビン状外部導電端子
２１をチップ・セレクト端子等容メモリ装置に固有な信
号端子とし、被膜状外部導電端子２２を人出方端子成る
いは電源端子等容メモリ装置に対する共通信号の端子と
する。そして上記のように半導体メモ１１・チップ２４
が実装されたチップ・キャリア２３上面に形成されてい
る通常構造の封止枠３３上に、鉛／錫合金等のろう材３
４を介して金属キャップ２５が気密にろう付けされてな
っている。The semiconductor memory chip 24 is a chip with a normal structure.
An internal pin-shaped external conductive terminal I is soldered onto the stage 29 via a gold/silicon alloy 80 or the like, and is connected to a pad terminal 31m through which a chip-specific signal is passed, such as a chip select terminal of the semiconductor memory chip 24, for example. Wiring 2
61 are connected to each other by a bonding wire 31 made of aluminum or the like. In addition, the pad terminal 31b, which is commonly wired to the memory chip such as the input/output terminal and the power supply terminal, and the internal upper part 4126-b connected to the film-like external conductive terminal 22 are connected by the bonding wire 32. In this structure, the ξ cylindrical external conductive terminal 21 is usually used as a signal terminal specific to the memory device, such as a chip select terminal, and the film-like external conductive terminal 22 is used as an output terminal or a power supply terminal. This is a common signal terminal for the equal capacity memory device. As mentioned above, the semiconductor memo 11 and the chip 24
A brazing material 3 such as a lead/tin alloy is placed on the sealing frame 33 of a normal structure formed on the top surface of the chip carrier 23 on which the chip carrier 23 is mounted.
A metal cap 25 is airtightly brazed through the cap 4.

本発明の構造を有する半導体装置は該半導体装置に配設
されたビン状外部導電端子を介して配線基板子に立てて
実装することができる。A semiconductor device having the structure of the present invention can be mounted upright on a wiring board via bottle-shaped external conductive terminals provided on the semiconductor device.

第４図は前記実施例１こ示した半導体メそす装置の実装
例を図示したもので、図中２１はピン状外部導電端子（
固有（ｉ最端子）、２２は被験状外部導電端子（共通信
号端子）、２３はセラミック・チップ・キャリア、２５
は金属キャップ、３４にはろう材、３５は半導体メモリ
装置、３６はセラミクス又はプラスチフス等からなる配
線基板、３７はスルーホール、３８は半田、３９は導Ｓ
を表わしている。FIG. 4 shows an example of mounting the semiconductor manufacturing device shown in the first embodiment, in which reference numeral 21 denotes a pin-shaped external conductive terminal (
Unique (i-most terminal), 22 is a test external conductive terminal (common signal terminal), 23 is a ceramic chip carrier, 25
34 is a metal cap, 34 is a brazing material, 35 is a semiconductor memory device, 36 is a wiring board made of ceramics or plastics, etc., 37 is a through hole, 38 is solder, and 39 is a conductive S
It represents.

即ち該第４図は最も実装密度を高めた実装例で、皺実装
構造に於ては、半導体メモリ装置３Ｓｔｉ上。That is, FIG. 4 shows a mounting example with the highest packaging density, and in the wrinkled mounting structure, it is on the semiconductor memory device 3Sti.

下面でお互いが豪し合う状態で配線基板３６上に立て並
べられ、各半導体メモリ装置３５のビン状外部導電端子
２１が配線基板３６に於ける所定のスルーホール３７に
さし込まれ半田付けされて固定される。そして各メモリ
装置３５に於ける共通信号端子である被膜状外部導電端
子２２上には各列毎にそれぞれ導４Ｉ３９からなる一連
の共通信号線が半田付けされる。The semiconductor memory devices 35 are arranged vertically on a wiring board 36 with their bottom surfaces facing each other, and the bottle-shaped external conductive terminals 21 of each semiconductor memory device 35 are inserted into predetermined through holes 37 in the wiring board 36 and soldered. Fixed. A series of common signal lines each consisting of a conductor 4I39 is soldered onto the film-like external conductive terminal 22, which is a common signal terminal in each memory device 35, for each column.

なお上記実施例に於てはビン状外部導電端子を２〔本〕
設けたが、鋏端子は必要に応じ何本でもさしつかえない
、又該ビン状外部導電端子は棒状で一端がキャリア内に
埋め込まれて形成されたものでも良い、又キャップはセ
ラミックスであっても良い、１に又本発明は金属パッケ
ージ、プラスチックパッケージにも適用することができ
る。In the above embodiment, two bottle-shaped external conductive terminals are used.
However, any number of scissor terminals may be used as required, and the bottle-shaped external conductive terminal may be formed in the form of a rod with one end embedded in the carrier, and the cap may be made of ceramics. , 1. The present invention can also be applied to metal packages and plastic packages.

（２））発明の効果 以上欽明したようにボ発明の構造を有する半導体装置鴨
、配線基析上に立てて実装することができる。そこで第
４図に示すような配線基板上への実装方法が可能であり
、図からも明らかな工うに従来の平面実装構造に比べて
実装置ｆを大幅に向上せしめることができる。(2)) Effects of the Invention As stated above, the semiconductor device having the structure of the invention can be mounted on a wiring substrate. Therefore, a mounting method on a wiring board as shown in FIG. 4 is possible, and as is clear from the figure, the actual device f can be greatly improved compared to the conventional planar mounting structure.

従って本発明は計算機システム等の高速化、小型化に対
して有効である。Therefore, the present invention is effective for speeding up and downsizing computer systems.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は従来構造の断面図（イ）及び下面図（ロ）、第
２図は従来の実装構造の断面模式図、第３図は本発明の
半導体装置に於ける一実施例の上面図（イ）。 上面図（イ）及び側面図（ロ）である。 図に於て、２１はビン状外部導電端子（固有信号端子）
、２２は被膜状外部導電端子（共通信号端子）、２３は
セラミック・チップ番キャリア、２４は半導体メモリ嗜
チップ、２５は金属キャップ、２６ｍ及び２６ｂは内部
配線、２７ｍ及び２７ｂは外部配線、２８は銀ろう、２
９はチップ・ステージ、３０は金／シリコン合金、３１
ａ及３１ｂはパッド端子、３２はボンディング・ワイヤ
、３３は封止枠、３４はろう材、３５は半導体メモリ装
置、３６＃′ｉ配線基板、３７はスルーホール、３８は
半田、３９は導線を示す。 死　１　四 第　２　図 １θFIG. 1 is a cross-sectional view (A) and bottom view (B) of a conventional structure, FIG. 2 is a schematic cross-sectional view of a conventional mounting structure, and FIG. 3 is a top view of an embodiment of the semiconductor device of the present invention. (stomach). They are a top view (a) and a side view (b). In the figure, 21 is a bottle-shaped external conductive terminal (specific signal terminal)
, 22 is a film-like external conductive terminal (common signal terminal), 23 is a ceramic chip carrier, 24 is a semiconductor memory chip, 25 is a metal cap, 26m and 26b are internal wirings, 27m and 27b are external wirings, 28 is a Silver wax, 2
9 is a chip stage, 30 is gold/silicon alloy, 31
a and 31b are pad terminals, 32 is a bonding wire, 33 is a sealing frame, 34 is a brazing material, 35 is a semiconductor memory device, 36 is a wiring board, 37 is a through hole, 38 is solder, and 39 is a conducting wire. show. Death 1 Fourth 2 Figure 1θ

Claims (1)

【特許請求の範囲】[Claims] 半導体チップが、−外部側面にビン状の外部導電端子を
有し、他の外部側面に被膜状の外部導電端子を有するチ
ップ・キャリアに実装されてなることを特許とする半導
体装置。A semiconductor device patented in which a semiconductor chip is mounted on a chip carrier having a bottle-shaped external conductive terminal on one external side and a film-like external conductive terminal on the other external side.
JP56211715A 1981-12-25 1981-12-25 Semiconductor device Granted JPS58112348A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56211715A JPS58112348A (en) 1981-12-25 1981-12-25 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56211715A JPS58112348A (en) 1981-12-25 1981-12-25 Semiconductor device

Publications (2)

Publication Number Publication Date
JPS58112348A true JPS58112348A (en) 1983-07-04
JPH0445981B2 JPH0445981B2 (en) 1992-07-28

Family

ID=16610394

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56211715A Granted JPS58112348A (en) 1981-12-25 1981-12-25 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS58112348A (en)

Cited By (27)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5943556A (en) * 1982-09-03 1984-03-10 Matsushita Electric Ind Co Ltd Forming method for end surface electrode
JPS60181072U (en) * 1984-05-12 1985-12-02 イビデン株式会社 Printed wiring board for chip mounting
US4939568A (en) * 1986-03-20 1990-07-03 Fujitsu Limited Three-dimensional integrated circuit and manufacturing method thereof
US5091762A (en) * 1988-07-05 1992-02-25 Kabushiki Kaisha Toshiba Semiconductor memory device with a 3-dimensional structure
US5369058A (en) * 1993-03-29 1994-11-29 Staktek Corporation Warp-resistent ultra-thin integrated circuit package fabrication method
US5367766A (en) * 1990-08-01 1994-11-29 Staktek Corporation Ultra high density integrated circuit packages method
US5377077A (en) * 1990-08-01 1994-12-27 Staktek Corporation Ultra high density integrated circuit packages method and apparatus
US5420751A (en) * 1990-08-01 1995-05-30 Staktek Corporation Ultra high density modular integrated circuit package
US5446620A (en) * 1990-08-01 1995-08-29 Staktek Corporation Ultra high density integrated circuit packages
US5448450A (en) * 1991-08-15 1995-09-05 Staktek Corporation Lead-on-chip integrated circuit apparatus
US5455740A (en) * 1994-03-07 1995-10-03 Staktek Corporation Bus communication system for stacked high density integrated circuit packages
US5475920A (en) * 1990-08-01 1995-12-19 Burns; Carmen D. Method of assembling ultra high density integrated circuit packages
US5484959A (en) * 1992-12-11 1996-01-16 Staktek Corporation High density lead-on-package fabrication method and apparatus
US5499160A (en) * 1990-08-01 1996-03-12 Staktek Corporation High density integrated circuit module with snap-on rail assemblies
US5541812A (en) * 1995-05-22 1996-07-30 Burns; Carmen D. Bus communication system for stacked high density integrated circuit packages having an intermediate lead frame
US5572065A (en) * 1992-06-26 1996-11-05 Staktek Corporation Hermetically sealed ceramic integrated circuit heat dissipating package
US5588205A (en) * 1995-01-24 1996-12-31 Staktek Corporation Method of manufacturing a high density integrated circuit module having complex electrical interconnect rails
US5644161A (en) * 1993-03-29 1997-07-01 Staktek Corporation Ultra-high density warp-resistant memory module
FR2747510A1 (en) * 1996-04-15 1997-10-17 Nec Corp LSI electronic circuit support assembly
US5801437A (en) * 1993-03-29 1998-09-01 Staktek Corporation Three-dimensional warp-resistant integrated circuit module method and apparatus
US5945732A (en) * 1997-03-12 1999-08-31 Staktek Corporation Apparatus and method of manufacturing a warp resistant thermally conductive integrated circuit package
US6025642A (en) * 1995-08-17 2000-02-15 Staktek Corporation Ultra high density integrated circuit packages
US6205654B1 (en) 1992-12-11 2001-03-27 Staktek Group L.P. Method of manufacturing a surface mount package
US6572387B2 (en) 1999-09-24 2003-06-03 Staktek Group, L.P. Flexible circuit connector for stacked chip module
US6576992B1 (en) 2001-10-26 2003-06-10 Staktek Group L.P. Chip scale stacking system and method
US6806120B2 (en) 2001-03-27 2004-10-19 Staktek Group, L.P. Contact member stacking system and method
KR100800140B1 (en) 2005-06-27 2008-02-01 주식회사 하이닉스반도체 Package stack

Cited By (47)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5943556A (en) * 1982-09-03 1984-03-10 Matsushita Electric Ind Co Ltd Forming method for end surface electrode
JPS60181072U (en) * 1984-05-12 1985-12-02 イビデン株式会社 Printed wiring board for chip mounting
US4939568A (en) * 1986-03-20 1990-07-03 Fujitsu Limited Three-dimensional integrated circuit and manufacturing method thereof
US5091762A (en) * 1988-07-05 1992-02-25 Kabushiki Kaisha Toshiba Semiconductor memory device with a 3-dimensional structure
US5420751A (en) * 1990-08-01 1995-05-30 Staktek Corporation Ultra high density modular integrated circuit package
US6168970B1 (en) 1990-08-01 2001-01-02 Staktek Group L.P. Ultra high density integrated circuit packages
US5367766A (en) * 1990-08-01 1994-11-29 Staktek Corporation Ultra high density integrated circuit packages method
US5377077A (en) * 1990-08-01 1994-12-27 Staktek Corporation Ultra high density integrated circuit packages method and apparatus
US5499160A (en) * 1990-08-01 1996-03-12 Staktek Corporation High density integrated circuit module with snap-on rail assemblies
US5446620A (en) * 1990-08-01 1995-08-29 Staktek Corporation Ultra high density integrated circuit packages
US5566051A (en) * 1990-08-01 1996-10-15 Staktek Corporation Ultra high density integrated circuit packages method and apparatus
US6049123A (en) * 1990-08-01 2000-04-11 Staktek Corporation Ultra high density integrated circuit packages
US5475920A (en) * 1990-08-01 1995-12-19 Burns; Carmen D. Method of assembling ultra high density integrated circuit packages
US5561591A (en) * 1990-08-01 1996-10-01 Staktek Corporation Multi-signal rail assembly with impedance control for a three-dimensional high density integrated circuit package
US5550711A (en) * 1990-08-01 1996-08-27 Staktek Corporation Ultra high density integrated circuit packages
US5543664A (en) * 1990-08-01 1996-08-06 Staktek Corporation Ultra high density integrated circuit package
US5448450A (en) * 1991-08-15 1995-09-05 Staktek Corporation Lead-on-chip integrated circuit apparatus
US5702985A (en) * 1992-06-26 1997-12-30 Staktek Corporation Hermetically sealed ceramic integrated circuit heat dissipating package fabrication method
US5572065A (en) * 1992-06-26 1996-11-05 Staktek Corporation Hermetically sealed ceramic integrated circuit heat dissipating package
US5631193A (en) * 1992-12-11 1997-05-20 Staktek Corporation High density lead-on-package fabrication method
US5484959A (en) * 1992-12-11 1996-01-16 Staktek Corporation High density lead-on-package fabrication method and apparatus
US6205654B1 (en) 1992-12-11 2001-03-27 Staktek Group L.P. Method of manufacturing a surface mount package
US5864175A (en) * 1993-03-29 1999-01-26 Staktek Corporation Wrap-resistant ultra-thin integrated circuit package fabrication method
US5895232A (en) * 1993-03-29 1999-04-20 Staktek Corporation Three-dimensional warp-resistant integrated circuit module method and apparatus
US5581121A (en) * 1993-03-29 1996-12-03 Staktek Corporation Warp-resistant ultra-thin integrated circuit package
US5369058A (en) * 1993-03-29 1994-11-29 Staktek Corporation Warp-resistent ultra-thin integrated circuit package fabrication method
US6194247B1 (en) 1993-03-29 2001-02-27 Staktek Group L.P. Warp-resistent ultra-thin integrated circuit package fabrication method
US5644161A (en) * 1993-03-29 1997-07-01 Staktek Corporation Ultra-high density warp-resistant memory module
US5369056A (en) * 1993-03-29 1994-11-29 Staktek Corporation Warp-resistent ultra-thin integrated circuit package fabrication method
US5978227A (en) * 1993-03-29 1999-11-02 Staktek Corporation Integrated circuit packages having an externally mounted lead frame having bifurcated distal lead ends
US5801437A (en) * 1993-03-29 1998-09-01 Staktek Corporation Three-dimensional warp-resistant integrated circuit module method and apparatus
US5828125A (en) * 1993-03-29 1998-10-27 Staktek Corporation Ultra-high density warp-resistant memory module
US5843807A (en) * 1993-03-29 1998-12-01 Staktek Corporation Method of manufacturing an ultra-high density warp-resistant memory module
US5493476A (en) * 1994-03-07 1996-02-20 Staktek Corporation Bus communication system for stacked high density integrated circuit packages with bifurcated distal lead ends
US5552963A (en) * 1994-03-07 1996-09-03 Staktek Corporation Bus communication system for stacked high density integrated circuit packages
US5455740A (en) * 1994-03-07 1995-10-03 Staktek Corporation Bus communication system for stacked high density integrated circuit packages
US5479318A (en) * 1994-03-07 1995-12-26 Staktek Corporation Bus communication system for stacked high density integrated circuit packages with trifurcated distal lead ends
US5588205A (en) * 1995-01-24 1996-12-31 Staktek Corporation Method of manufacturing a high density integrated circuit module having complex electrical interconnect rails
US5541812A (en) * 1995-05-22 1996-07-30 Burns; Carmen D. Bus communication system for stacked high density integrated circuit packages having an intermediate lead frame
US6025642A (en) * 1995-08-17 2000-02-15 Staktek Corporation Ultra high density integrated circuit packages
FR2747510A1 (en) * 1996-04-15 1997-10-17 Nec Corp LSI electronic circuit support assembly
US6190939B1 (en) 1997-03-12 2001-02-20 Staktek Group L.P. Method of manufacturing a warp resistant thermally conductive circuit package
US5945732A (en) * 1997-03-12 1999-08-31 Staktek Corporation Apparatus and method of manufacturing a warp resistant thermally conductive integrated circuit package
US6572387B2 (en) 1999-09-24 2003-06-03 Staktek Group, L.P. Flexible circuit connector for stacked chip module
US6806120B2 (en) 2001-03-27 2004-10-19 Staktek Group, L.P. Contact member stacking system and method
US6576992B1 (en) 2001-10-26 2003-06-10 Staktek Group L.P. Chip scale stacking system and method
KR100800140B1 (en) 2005-06-27 2008-02-01 주식회사 하이닉스반도체 Package stack

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