JPS58103252A - Unidirectional transmitting device - Google Patents

Abstract

PURPOSE:To transmit data independently by each slave device when the data is stopped and to increase the transmitting speed of the data, by providing a timer for detecting the stoppage of the input data and a date producing circuit which gives the own data to a transmitting circuit in response to the time-up of a timer to each slave device. CONSTITUTION:The data given from a terminal device TE is received at a slave device SE1, and the own transmission data is added to the data given from the TE at the device SE1. These data are fed to the next slave device SE2 to be relayed successively to the slave device SE3. This relayed data is transmitted to a master device E; A timer TIM is provided to each of the device SE1-ES3 to detect the stoppage of the input data to a receiving circuit RC. The time-up output of the timer TIM is applied to a data producing circuit DG, and the signal that is transmitted from a transmitting circuit SC in accordance with the time-up is produced from the data given from a code reproducing circuit CRG and then applied to an OR circuit G. Then the own produced data is transmitted when the input data is discontinued for a prescribed period or longer. Thus the data transmitting speed is increased.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides a terminal that is arranged in a parent device, a child device, and a terminal!
fi1. The present invention relates to an improvement of a one-way transmission device in which data is connected in series through one transmission line each, and data is transmitted from the terminal device side to the parent device side.

FIG. 1 is a block diagram showing a mature example of such a one-way transmission device, in which a terminal device TE is arranged at the terminal, and a terminal device Tg, child devices 1tSEl to SEn, and a parent device ME are each arranged as one unit. The data periodically generated by the code generation circuit CDGt is transmitted from the terminal bag TE via the transmission circuit Set, which is connected in series with the transmission line Lt=Ln of the system. ing.

This data is received by the slave device SEl! l! l path 1'
It is received by LC1, converted into a regular waveform by the code reproducing circuits CR and Ul, and then given to the transmission image @S C1 via the OR game (Gl), which sends it to the parent device ME side. The circuit RC1 sends out a start signal SS in response to the completion of the input data, and supplies it to the data creation circuit DGl, and in response to the start signal Sg, the data creation circuit D (1l sends out its own data). ,OR
In order to provide the input data to the transmission circuit SC1 via the gate O1, the input data is relayed (, 4) and then its own data is transmitted to the parent device ME side.

Note that the above-mentioned operation is the same in the slave devices 8Es-8FSn, and in the slave device 8En, the terminal device Tli
Starting with the data from
A signal consisting of n data serially is transmitted, which is sequentially received by the receiving circuit RCmK of the parent device ME, and sequentially stored in each address of the memory MMm, and these operations are performed by the terminal device TT7A. It is repeated according to the data sent from.

However, in the case of the configuration shown in FIG.
Any of n, or terminal device TE to child device 8E
If a failure occurs in any one of the 1-813n systems, the data transmission function of the entire system will be lost, resulting in a serious drawback.

As a countermeasure for this drawback, the one shown in the block diagram of Fig. 2 has been proposed.
In addition to transmitting data independently, input data is stored once and then transmitted together with its own data.

That is, the data created by the data creation circuit DGt of the terminal device TH is transmitted by the transmission circuit Set and received by the reception circuit RC1 of the child device 8B1, but is once stored in the memory MMl&l(+'). After the data generation circuit DGt sends out the data, the contents of the memory MMt are read out in response to the readout signal 8B given, and then sent to the transmission circuit 8 via the OR game (Gl).
It is to be sent to C1.

Therefore, the data of the slave device 8B1 is stored in the data creation circuit D.
According to the periodic operation of G1, input data is transmitted via OR gate Gt and transmission circuit 8C1, and input data is subsequently transmitted to slave devices 8Bm~
By repeating the same operation in 8Em, the parent device ME has the terminal device @TE and each child device 8F1-8E.
Each data of n is given.

Therefore, since each slave device 8Bl-8EnK1 performs its own transmission operation, even if a failure occurs in any of the transmission lines Lt, Ll-Ln or slave devices 8El-8hn, the operation after the failed part is There is no problem, and the data transmission function after the failed part is maintained.

However, in the case of the configuration shown in FIG. 2, each child device 8Bt
- Since data is accumulated in 8gn, it takes a long time for the data from the terminal device TE and the child device on the TE side to reach the parent device ME, which has the disadvantage of reducing the data transmission speed. It is occurring.

The present invention has the purpose of fundamentally solving the above drawbacks of the conventional technology, and based on the premise of the configuration shown in FIG. By providing each child device with a data creation circuit that sends its own data to the transmission circuit in response to the input data, each child device independently transmits data when input data stops, which is extremely effective. This provides a unique one-way transmission device.

Hereinafter, the present invention will be explained in detail with reference to FIG. 3 and subsequent figures showing embodiments.

FIG. 3 is a block diagram showing the slave station SB, which is provided with a timer TIM in addition to that shown in FIG.
The data creation circuit D() is assumed to periodically send out its own data in response to the time-up signal 8TU of the timer TIM.

Further, when the receiving circuit RC receives input data, it sends out a reset signal 8 ns, which resets the timer TIM, and in response to the start signal 8BTl sent out when the code regeneration circuit CRG finishes sending out the input data, Start signal 88 sent by data creation circuit DG
The timer TIM is activated according to the T-crow.

Note that the data creation circuit DG receives the -start signal 88Tl.
It also sends out its own data and gives it to the transmission circuit SC via the OR gate G. Therefore, when input data is given, the timer TIM
is reset and enters a standby state, but input data is sent out from the code regeneration circuit CRG, and when this ends, the timer TIM is started at the same time as data is sent out from the data creation circuit DG.

However, if the input data is repeatedly given before the timer TIM times up, the timer TIM will not time up and the time-up signal 8 U will not be generated.
Data is exited only by yt, and as in FIG. 1, the transmitting circuit SC serially transmits its own data following the input data.

On the other hand, if the input data stops for a certain period or more, the timer TIM times up and sends out the time-up signal 8TU as a detection output, so the data is sent out from the data creation circuit DG and given to the transmission circuit 8C.
By being transmitted from this point, even if the input data stops due to some kind of failure, the own data will be periodically and repeatedly transmitted, and the data between the next child device or the parent device ME will be transmitted. Transmission is successful.

Therefore, for example, in the case of the device configuration shown in FIG. 4, data transmission is performed as shown in the timing chart of FIG.

That is, if all systems are normal, the data Dta from the terminal device TE is received by the child device SBI, relayed and transmitted, and subsequently sent to the child device 8Ex.
The data Dxa of 8Bm is also transmitted, and similarly
, 8Em also relays and own data Dma,
Dsa is transmitted, and the parent device ME sends the data Dt.
m to Daa are received in series.

Furthermore, if the data Dtb is transmitted within a certain period T determined according to the time set in the timer TIM, and this is received by the child device 8Bl, the timer TIM is reset. D
Transmission of tb to Dsb is performed.

On the other hand, if a failure occurs in the transmission line Lt, the data Dt
c is no longer received by the child device SHt, and if this continues for a certain period of time or more, the child device 8El automatically starts transmitting data DIC in response to the time-up of the timer TIM, and the data from the child device 8El onwards. D1
cmDsc is transmitted normally, and the functionality of the entire device is maintained except for the terminal device TI.

Note that as the timer TIM, an integrating circuit, a counter that counts clock pulses, etc. may be used, and the data creation circuit DGK is one that adds a timing pulse generator, etc., and uses this K to periodically send out data. And it is sufficient.

However, the number of child devices 8Bl-8gn is determined depending on the conditions, and the configuration of the parent device ME is also determined according to the situation.
Various modifications are possible, such as the ability to select any frequency signal, pulse signal, or the like.

As is clear from the above explanation, according to the present invention, the reliability of a unidirectional transmission system is greatly improved with a simple configuration without reducing the transmission speed, and therefore, it is noticeable in unidirectional transmission devices for various uses. exhibits an effect.

[Brief explanation of the drawing]

1 and 2 are block diagrams showing a conventional example, FIG. 3 is a block diagram showing an embodiment of the present invention, FIG. 4 is a block diagram showing an example of the device configuration, and FIG. 5 is the data in FIG. 4. 5 is a timing chart showing transmission status. ME... Parent device, 8 E l-8E n@... Child device, T' B @ 1 〇 〇 Terminal device, L t,
Lt~Iin 11 @...Transmission line, TIM-...Timer, DC)...Data creation circuit, SC...
Transmission circuit, 8tu...Time-up signal, T...
・For a certain period of time. Patent applicant: Kyosan Seisakusho Co., Ltd. Masaki Yamakawa (and 1 other person)

Claims (1)

[Claims] One parent device, one child device, and one terminal device assigned to the terminal.
They are connected in series through the transmission line of the system, and data is periodically transmitted from the terminal bag device, and the input data is relayed in the front six child devices and transmitted to the front mla device, and the input data is transmitted. A one-way transmission device that later transmits its own data to the parent device includes a tandemer that detects that the input data has stopped for a certain period of time or more, and a tandemor that provides its own data to the latent damage circuit according to the timer time-up and transmits it. A one-way transmission device characterized in that the child device is provided with a data creation circuit for generating data.