JPS579176A - Synchronizing separation circuit - Google Patents
Synchronizing separation circuitInfo
- Publication number
- JPS579176A JPS579176A JP8315980A JP8315980A JPS579176A JP S579176 A JPS579176 A JP S579176A JP 8315980 A JP8315980 A JP 8315980A JP 8315980 A JP8315980 A JP 8315980A JP S579176 A JPS579176 A JP S579176A
- Authority
- JP
- Japan
- Prior art keywords
- synchronizing
- signal
- output
- pulse
- synchronizing signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/04—Synchronising
- H04N5/08—Separation of synchronising signals from picture signals
Landscapes
- Engineering & Computer Science (AREA)
- Multimedia (AREA)
- Signal Processing (AREA)
- Synchronizing For Television (AREA)
Abstract
PURPOSE:To obtain an output synchronizing signal in phase with an input synchronizing signal without being affected with noise, by constituting an output synchronizing signal through the addition and pickup of an input synchronizing signal and a signal having a phase difference delayed for a given time from n-times synchronizing signal period. CONSTITUTION:A pair of synchronizing signals S1, S2 having a phase difference of 1H-alpha (where; H is horizontal synchronism, alpha is a given time, 0<alpha<tau, and tau is the time width of the horizontal synchronizing pulse) are outputted from a delay means 2 to which an input horizontal synchronizing signal is applied. Further, the signals S1 and S2 are applied to an addition circuit 3 to obtain an addition output S3. Thus, in the output S3, each synchronizing pulse D of the signals S1, S2 is added, and a pulse section D' in which the level is twice the level of the synchronizing pulse is produced. The level of noise N is kept the same. Further, the output S3 is applied to a slice circuit 4 to obtain a synchronizing signal S4. The phase of a synchronizing pulse D'' of the signal S4 is coincided with the phase of the synchronizing pulse D of the signal S1.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP8315980A JPS579176A (en) | 1980-06-19 | 1980-06-19 | Synchronizing separation circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP8315980A JPS579176A (en) | 1980-06-19 | 1980-06-19 | Synchronizing separation circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS579176A true JPS579176A (en) | 1982-01-18 |
Family
ID=13794460
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP8315980A Pending JPS579176A (en) | 1980-06-19 | 1980-06-19 | Synchronizing separation circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS579176A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2644025A1 (en) * | 1989-03-03 | 1990-09-07 | Thomson Csf | Device for extracting "3 state" pulses in a noisy medium |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5126768A (en) * | 1974-08-28 | 1976-03-05 | Tokyo Shibaura Electric Co | Kaiheibuta no anzensochi |
-
1980
- 1980-06-19 JP JP8315980A patent/JPS579176A/en active Pending
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5126768A (en) * | 1974-08-28 | 1976-03-05 | Tokyo Shibaura Electric Co | Kaiheibuta no anzensochi |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2644025A1 (en) * | 1989-03-03 | 1990-09-07 | Thomson Csf | Device for extracting "3 state" pulses in a noisy medium |
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