JPS5787241A - Phase synchronizing circuit for optional frequency conversion - Google Patents

Phase synchronizing circuit for optional frequency conversion

Info

Publication number
JPS5787241A
JPS5787241A JP55163151A JP16315180A JPS5787241A JP S5787241 A JPS5787241 A JP S5787241A JP 55163151 A JP55163151 A JP 55163151A JP 16315180 A JP16315180 A JP 16315180A JP S5787241 A JPS5787241 A JP S5787241A
Authority
JP
Japan
Prior art keywords
phase
output
gate
voltage control
control oscillator
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP55163151A
Other languages
Japanese (ja)
Other versions
JPS6333739B2 (en
Inventor
Hiroshi Okano
Hideo Sakata
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP55163151A priority Critical patent/JPS5787241A/en
Publication of JPS5787241A publication Critical patent/JPS5787241A/en
Publication of JPS6333739B2 publication Critical patent/JPS6333739B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
    • H03L7/197—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division
    • H03L7/199—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division with reset of the frequency divider or the counter, e.g. for assuring initial synchronisation

Landscapes

  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)

Abstract

PURPOSE:To prevent the step-out of synchronization, by selecting one pulse from the output of a voltage control oscillator by a gate circuit and by substituting a large phase step of the input by a small phase step corresponding to the clock interval of the oscillation frequency. CONSTITUTION:An output signal 2a obtained by dividing an input signal 1 of a frequency f1 in a counter 2 by 1/m is used as a trigger to generate a gate 8a at a proper time in a gate circuit 8. A pulse of fO/n is selected from an output 7 of a voltage control oscillator 5' by this gate 8a and is inputted to a phase comparator 3 as an output 8b of the gate circuit 8. Phases of outputs 2a and 8b are compared with each other by the phase comparator 3; and if a phase error is detected, the oscillation frequency of the voltage control oscillator 5' is corrected by smoothing in an LPF4, and the phase is automatically controlled to eliminate the phase error. Consequently, even if a large step input is inputted to the phase synchronizing circuit, the step-out of synchronization is prevented.
JP55163151A 1980-11-18 1980-11-18 Phase synchronizing circuit for optional frequency conversion Granted JPS5787241A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55163151A JPS5787241A (en) 1980-11-18 1980-11-18 Phase synchronizing circuit for optional frequency conversion

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55163151A JPS5787241A (en) 1980-11-18 1980-11-18 Phase synchronizing circuit for optional frequency conversion

Publications (2)

Publication Number Publication Date
JPS5787241A true JPS5787241A (en) 1982-05-31
JPS6333739B2 JPS6333739B2 (en) 1988-07-06

Family

ID=15768186

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55163151A Granted JPS5787241A (en) 1980-11-18 1980-11-18 Phase synchronizing circuit for optional frequency conversion

Country Status (1)

Country Link
JP (1) JPS5787241A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60167525A (en) * 1984-02-10 1985-08-30 Hitachi Ltd Generating circuit of internal clock
JPS6346013A (en) * 1986-08-13 1988-02-26 Sony Corp Phase locked loop circuit
JPH02226913A (en) * 1989-02-28 1990-09-10 Fujitsu Ltd Dead lock phenomenon prevention circuit for pll including digital mixer

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS51105751A (en) * 1975-03-14 1976-09-18 Nippon Electron Optics Lab Fueizu rotsuku ruupukairo

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS51105751A (en) * 1975-03-14 1976-09-18 Nippon Electron Optics Lab Fueizu rotsuku ruupukairo

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60167525A (en) * 1984-02-10 1985-08-30 Hitachi Ltd Generating circuit of internal clock
JPS6346013A (en) * 1986-08-13 1988-02-26 Sony Corp Phase locked loop circuit
JPH02226913A (en) * 1989-02-28 1990-09-10 Fujitsu Ltd Dead lock phenomenon prevention circuit for pll including digital mixer
JP2549431B2 (en) * 1989-02-28 1996-10-30 富士通株式会社 Deadlock phenomenon prevention circuit of PLL including digital mixer

Also Published As

Publication number Publication date
JPS6333739B2 (en) 1988-07-06

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