JPS5766646A - Manufacture of resin sealed type semiconductor device - Google Patents

Manufacture of resin sealed type semiconductor device

Info

Publication number
JPS5766646A
JPS5766646A JP14273280A JP14273280A JPS5766646A JP S5766646 A JPS5766646 A JP S5766646A JP 14273280 A JP14273280 A JP 14273280A JP 14273280 A JP14273280 A JP 14273280A JP S5766646 A JPS5766646 A JP S5766646A
Authority
JP
Japan
Prior art keywords
resin
lead frames
type semiconductor
manufacture
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14273280A
Other languages
Japanese (ja)
Inventor
Saburo Ogawara
Takeshi Yoneyama
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP14273280A priority Critical patent/JPS5766646A/en
Publication of JPS5766646A publication Critical patent/JPS5766646A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/565—Moulds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

PURPOSE:To reduce the system cost with respect to the manufacture of a resin sealed type semiconductor device by arranging lead frames within an effective area of a metal mold along the carrying direction to mold with resin. CONSTITUTION:Lead frames 18 are arranged respectively one by one from the starting ends to the terminals of cavities 14, 14' provided along the carrying direction of the lead frames 18 of a metal mold, and after seminconductor elements 19 of respective lead frames 18 being accommodated in the cavities 14, 14', resin is injected in a pot of the metal mold, thereby the resin is molded. After that, said resin is carried to a post-cure device, where the post cure for the resin is performed. Further, cutting and processing for respective lead frames 18 are performed, and a plurality of resin sealing type semiconductor devices wherein the semiconductor elements are sealed with resin layers are obrained.
JP14273280A 1980-10-13 1980-10-13 Manufacture of resin sealed type semiconductor device Pending JPS5766646A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14273280A JPS5766646A (en) 1980-10-13 1980-10-13 Manufacture of resin sealed type semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14273280A JPS5766646A (en) 1980-10-13 1980-10-13 Manufacture of resin sealed type semiconductor device

Publications (1)

Publication Number Publication Date
JPS5766646A true JPS5766646A (en) 1982-04-22

Family

ID=15322286

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14273280A Pending JPS5766646A (en) 1980-10-13 1980-10-13 Manufacture of resin sealed type semiconductor device

Country Status (1)

Country Link
JP (1) JPS5766646A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2580982A1 (en) * 1984-03-06 1986-10-31 Asm Fico Tooling SYSTEM AND METHOD FOR AUTOMATIC MOLDING WITH CONTINUOUS CYCLES

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2580982A1 (en) * 1984-03-06 1986-10-31 Asm Fico Tooling SYSTEM AND METHOD FOR AUTOMATIC MOLDING WITH CONTINUOUS CYCLES

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