JPS5755445A - Communication control processor - Google Patents

Communication control processor

Info

Publication number
JPS5755445A
JPS5755445A JP55129587A JP12958780A JPS5755445A JP S5755445 A JPS5755445 A JP S5755445A JP 55129587 A JP55129587 A JP 55129587A JP 12958780 A JP12958780 A JP 12958780A JP S5755445 A JPS5755445 A JP S5755445A
Authority
JP
Japan
Prior art keywords
processors
storage device
protocol
communication control
processor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP55129587A
Other languages
Japanese (ja)
Inventor
Yoshizo Fukuhara
Kenji Koyama
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP55129587A priority Critical patent/JPS5755445A/en
Publication of JPS5755445A publication Critical patent/JPS5755445A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/10—Program control for peripheral devices
    • G06F13/12—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
    • G06F13/124—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware is a sequential transfer control unit, e.g. microprocessor, peripheral processor or state-machine
    • G06F13/128—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware is a sequential transfer control unit, e.g. microprocessor, peripheral processor or state-machine for dedicated transfers to a network

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multi Processors (AREA)
  • Computer And Data Communications (AREA)
  • Communication Control (AREA)

Abstract

PURPOSE:To make the protocol processing efficient, by connecting a plurality of processors in series and executing the processing of protocol of each layer for the architecture of computer network corresponding to each processor. CONSTITUTION:The processor consists of a plurality of processors 11-1N connected respectively in series, storage device groups 51-5N used by each processor exclusively, storage device control circuit groups 41-4N, storage device groups 61-6N commonly used for mutual communication by adjacent processors, storage device groups 71-7N commonly used with all the processors, and storage device control circuits 81-8M. With this constitution, the processors 11-1N execute the communication control protocol processing sequentially to incoming telegraphic messages, but the execution of protocol of each functional hierarchy at the communication control is sequentially executed for the protocol of adjacent hierarchy and irregular order of execution is avoided.
JP55129587A 1980-09-18 1980-09-18 Communication control processor Pending JPS5755445A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55129587A JPS5755445A (en) 1980-09-18 1980-09-18 Communication control processor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55129587A JPS5755445A (en) 1980-09-18 1980-09-18 Communication control processor

Publications (1)

Publication Number Publication Date
JPS5755445A true JPS5755445A (en) 1982-04-02

Family

ID=15013127

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55129587A Pending JPS5755445A (en) 1980-09-18 1980-09-18 Communication control processor

Country Status (1)

Country Link
JP (1) JPS5755445A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60151776A (en) * 1984-01-18 1985-08-09 Res Dev Corp Of Japan Composite computer system
JPS6238060A (en) * 1985-08-12 1987-02-19 Matsushita Graphic Commun Syst Inc Communication control equipment
JPS62117050A (en) * 1985-11-15 1987-05-28 Matsushita Graphic Commun Syst Inc Protocol processor
JPS6388661A (en) * 1986-10-01 1988-04-19 Matsushita Graphic Commun Syst Inc Communication controller

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60151776A (en) * 1984-01-18 1985-08-09 Res Dev Corp Of Japan Composite computer system
JPH02733B2 (en) * 1984-01-18 1990-01-09 Shingijutsu Kaihatsu Jigyodan
JPS6238060A (en) * 1985-08-12 1987-02-19 Matsushita Graphic Commun Syst Inc Communication control equipment
JPS62117050A (en) * 1985-11-15 1987-05-28 Matsushita Graphic Commun Syst Inc Protocol processor
JPS6388661A (en) * 1986-10-01 1988-04-19 Matsushita Graphic Commun Syst Inc Communication controller

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