JPS5752954A - Information processing equipment - Google Patents

Information processing equipment

Info

Publication number
JPS5752954A
JPS5752954A JP12825480A JP12825480A JPS5752954A JP S5752954 A JPS5752954 A JP S5752954A JP 12825480 A JP12825480 A JP 12825480A JP 12825480 A JP12825480 A JP 12825480A JP S5752954 A JPS5752954 A JP S5752954A
Authority
JP
Japan
Prior art keywords
interruption
signal
output
circuit
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP12825480A
Other languages
Japanese (ja)
Other versions
JPS614133B2 (en
Inventor
Mikio Handa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP12825480A priority Critical patent/JPS5752954A/en
Publication of JPS5752954A publication Critical patent/JPS5752954A/en
Publication of JPS614133B2 publication Critical patent/JPS614133B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/24—Handling requests for interconnection or transfer for access to input/output bus using interrupt

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)

Abstract

PURPOSE:To use numerous memory capacities under a direct control of a CPU, by supplying an assigned memory selecting signal to the memory when an interruption request is generated against the arithmetic processing device. CONSTITUTION:This equipment has a decoder 12 which selects one memory out of memories 13-23 and another decoder 24 which selects one memory out of memories 16-23. Outputs Q0-Q2 are initialized by a latch 25 through a reset signal from an arithmetic control 11, and data of data buses DB0-DB2 are latch output by an output signal of the circuit 11, and then, outputs A-B of an interruption controlling circuit 27 are latch output by an interruption accept signal INTA. Moreover, when an interruption instruction read signal IRD is output, an interruption instruction is output to the data bus from an interruption instruction circuit 26, and, when signals are input into an interruption request terminals INT0-INT7, an interruption request signal INT is input to the circuit 11 and outputs A-C are obtained by encoding the interruption request signal from the interruption controlling circuit 27.
JP12825480A 1980-09-16 1980-09-16 Information processing equipment Granted JPS5752954A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12825480A JPS5752954A (en) 1980-09-16 1980-09-16 Information processing equipment

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12825480A JPS5752954A (en) 1980-09-16 1980-09-16 Information processing equipment

Publications (2)

Publication Number Publication Date
JPS5752954A true JPS5752954A (en) 1982-03-29
JPS614133B2 JPS614133B2 (en) 1986-02-07

Family

ID=14980299

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12825480A Granted JPS5752954A (en) 1980-09-16 1980-09-16 Information processing equipment

Country Status (1)

Country Link
JP (1) JPS5752954A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5957357A (en) * 1982-09-27 1984-04-02 Fujitsu Ltd Multiple access system of storage device
JPS59230748A (en) * 1983-06-13 1984-12-25 凸版印刷株式会社 Decorative sheet
JPS59231661A (en) * 1983-06-13 1984-12-26 Fujitsu Ltd Bank control system accompanying program division

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5957357A (en) * 1982-09-27 1984-04-02 Fujitsu Ltd Multiple access system of storage device
JPS59230748A (en) * 1983-06-13 1984-12-25 凸版印刷株式会社 Decorative sheet
JPS59231661A (en) * 1983-06-13 1984-12-26 Fujitsu Ltd Bank control system accompanying program division

Also Published As

Publication number Publication date
JPS614133B2 (en) 1986-02-07

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