JPS5748833A - Gate circuit - Google Patents

Gate circuit

Info

Publication number
JPS5748833A
JPS5748833A JP55123246A JP12324680A JPS5748833A JP S5748833 A JPS5748833 A JP S5748833A JP 55123246 A JP55123246 A JP 55123246A JP 12324680 A JP12324680 A JP 12324680A JP S5748833 A JPS5748833 A JP S5748833A
Authority
JP
Japan
Prior art keywords
input device
inverter circuit
substrate
gate
increased
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP55123246A
Other languages
Japanese (ja)
Inventor
Kazuyuki Miyadera
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP55123246A priority Critical patent/JPS5748833A/en
Publication of JPS5748833A publication Critical patent/JPS5748833A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K19/00Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/094Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
    • H03K19/0944Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET
    • H03K19/09441Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET of the same canal type
    • H03K19/09443Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET of the same canal type using a combination of enhancement and depletion transistors
    • H03K19/09445Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET of the same canal type using a combination of enhancement and depletion transistors with active depletion transistors

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Electronic Switches (AREA)
  • Logic Circuits (AREA)

Abstract

PURPOSE:To increase the margin of noise, by providing a depletion type MOSFET between the source and ground of an input device of an inverter circuit of the 1st E/D type and connecting the output of the 2nd inverter circuit to the gate. CONSTITUTION:When a voltage between the source and substrate of an input device Q5 is increased, the apparent threshold voltage of the input device Q5 is increased by the substrate effect. In the gate circuit, a potential difference between the source and the substrate of the input device Q5 is produced with the depletion type MOSFETQ6 to produce the substrate effect. Thus, when the input signal is at low level, the apparent threshold voltage of the input device Q5 is increased and the noise margin is made greater. Since the gate of the MOSFETQ6 is connected to the output OUT of the 2nd inverter circuit, the input signal is in phase with the output of the 2nd inverter circuit, and the mutual conductance of the FETQ6 is changed by the input voltage.
JP55123246A 1980-09-05 1980-09-05 Gate circuit Pending JPS5748833A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55123246A JPS5748833A (en) 1980-09-05 1980-09-05 Gate circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55123246A JPS5748833A (en) 1980-09-05 1980-09-05 Gate circuit

Publications (1)

Publication Number Publication Date
JPS5748833A true JPS5748833A (en) 1982-03-20

Family

ID=14855818

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55123246A Pending JPS5748833A (en) 1980-09-05 1980-09-05 Gate circuit

Country Status (1)

Country Link
JP (1) JPS5748833A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5783930A (en) * 1980-11-12 1982-05-26 Fujitsu Ltd Buffer circuit
EP0140188A2 (en) * 1983-10-28 1985-05-08 Siemens Aktiengesellschaft C-MOS inverter
US4821409A (en) * 1981-10-26 1989-04-18 Burndy Corporation Electrical connection apparatus for flat conductor cables and similar articles
US4833775A (en) * 1981-10-26 1989-05-30 Burndy Corporation Electrical connection apparatus for flat conductor cables and similar articles
DE10229873B4 (en) * 2001-07-06 2005-07-07 Yazaki Corp. Puncture connection, and device and method for crimping a puncture connection

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS522160A (en) * 1975-06-24 1977-01-08 Hitachi Ltd Signal transmission circuit
JPS5269545A (en) * 1975-12-08 1977-06-09 Hitachi Ltd Oscillation circuit

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS522160A (en) * 1975-06-24 1977-01-08 Hitachi Ltd Signal transmission circuit
JPS5269545A (en) * 1975-12-08 1977-06-09 Hitachi Ltd Oscillation circuit

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5783930A (en) * 1980-11-12 1982-05-26 Fujitsu Ltd Buffer circuit
US4821409A (en) * 1981-10-26 1989-04-18 Burndy Corporation Electrical connection apparatus for flat conductor cables and similar articles
US4833775A (en) * 1981-10-26 1989-05-30 Burndy Corporation Electrical connection apparatus for flat conductor cables and similar articles
EP0140188A2 (en) * 1983-10-28 1985-05-08 Siemens Aktiengesellschaft C-MOS inverter
DE10229873B4 (en) * 2001-07-06 2005-07-07 Yazaki Corp. Puncture connection, and device and method for crimping a puncture connection

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