JPS5746559A - Frequency deviation demodulating system - Google Patents

Frequency deviation demodulating system

Info

Publication number
JPS5746559A
JPS5746559A JP55123045A JP12304580A JPS5746559A JP S5746559 A JPS5746559 A JP S5746559A JP 55123045 A JP55123045 A JP 55123045A JP 12304580 A JP12304580 A JP 12304580A JP S5746559 A JPS5746559 A JP S5746559A
Authority
JP
Japan
Prior art keywords
output signal
digital
signal
discriminating circuit
inputted
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP55123045A
Other languages
Japanese (ja)
Inventor
Moichi Hirasawa
Akira Horiguchi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP55123045A priority Critical patent/JPS5746559A/en
Priority to US06/293,266 priority patent/US4485347A/en
Publication of JPS5746559A publication Critical patent/JPS5746559A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L27/00—Modulated-carrier systems
    • H04L27/10—Frequency-modulated carrier systems, i.e. using frequency-shift keying
    • H04L27/14—Demodulator circuits; Receiver circuits
    • H04L27/156—Demodulator circuits; Receiver circuits with demodulation using temporal properties of the received signal, e.g. detecting pulse width
    • H04L27/1563—Demodulator circuits; Receiver circuits with demodulation using temporal properties of the received signal, e.g. detecting pulse width using transition or level detection
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L27/00—Modulated-carrier systems
    • H04L27/10—Frequency-modulated carrier systems, i.e. using frequency-shift keying
    • H04L27/14—Demodulator circuits; Receiver circuits
    • H04L27/156—Demodulator circuits; Receiver circuits with demodulation using temporal properties of the received signal, e.g. detecting pulse width
    • H04L27/1566—Demodulator circuits; Receiver circuits with demodulation using temporal properties of the received signal, e.g. detecting pulse width using synchronous sampling

Abstract

PURPOSE:To digitize the system overall to obtain a superior characteristic without any temperature drift and little signal distortion and signal error, by discriminating the duty factor of the output signal of a digital phase lock loop (DPLL) digitally. CONSTITUTION:The duty factor of an output signal 10 of a DPLL5 is discriminated digitally in a digital discriminating circuit 12. That is, the zero crossing waveform of a binary frequency deviation modulation signal 9 is inputted to the DPLL5, and the output signal 10 is inputted to the digital discriminating circuit 12, and the duty factor of the output signal is discriminated on a basis of a high-speed sample and its pulse count value. An output 14 of the digital discriminating circuit 12 is inputted to a converting circuit 13 and is not only converted to corresponding DC components by the repeat period of the pulse of the output signal 10 but also outputted to a discriminating circuit 7 through a digital primary low pass filter. The discriminating circuit 7 discriminates whether an output signal 11 is larger than a constant threshold or not, thereby outputting a demodulation data signal 8.
JP55123045A 1980-09-04 1980-09-04 Frequency deviation demodulating system Pending JPS5746559A (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP55123045A JPS5746559A (en) 1980-09-04 1980-09-04 Frequency deviation demodulating system
US06/293,266 US4485347A (en) 1980-09-04 1981-08-17 Digital FSK demodulator

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55123045A JPS5746559A (en) 1980-09-04 1980-09-04 Frequency deviation demodulating system

Publications (1)

Publication Number Publication Date
JPS5746559A true JPS5746559A (en) 1982-03-17

Family

ID=14850838

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55123045A Pending JPS5746559A (en) 1980-09-04 1980-09-04 Frequency deviation demodulating system

Country Status (1)

Country Link
JP (1) JPS5746559A (en)

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