JPS5741052A - Burst error correcting system applied to recording device or transmission device of series data byte - Google Patents
Burst error correcting system applied to recording device or transmission device of series data byteInfo
- Publication number
- JPS5741052A JPS5741052A JP11641180A JP11641180A JPS5741052A JP S5741052 A JPS5741052 A JP S5741052A JP 11641180 A JP11641180 A JP 11641180A JP 11641180 A JP11641180 A JP 11641180A JP S5741052 A JPS5741052 A JP S5741052A
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- syndrome
- exclusive
- register
- circulating
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
- H04L1/0056—Systems characterized by the type of code used
- H04L1/0057—Block codes
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Error Detection And Correction (AREA)
Abstract
PURPOSE:To correct an error with high reliablity, by adding a parity check byte and a circulating check byte to a data at the side of an encoder, generating a parity syndrome and a circulating syndrome at the side of a decoder, and after that, comparing them. CONSTITUTION:At the side of an encoder, a parity check byte ECC1 is generated by an exclusive OR circuit 1 and a register 2. In the same way, to input information bytes B1-B16, a circulating check byte ECC2 is generated by an exclusive OR circuit 3, a register 4 and a T-multiplier 5. A multiplexer 6 arranges in time series an information byte and both the check bytes, and outputs them. At the side of a decoder, a parity syndrome S1 is generated by an exclusive OR circuit 11 and a register 12. Also, a circulating syndrome S2 is generated by an exclusive OR circuit 13 and a register 14. The syndrome S2 is provided to a register 17, is T-multiplied by a T- multiplier 18, and after that, is provided to a comparing circuit consisting of an exclusive OR circuit 19 and an AND circuit 20, in which it is compared with the syndrome S1.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP11641180A JPS5741052A (en) | 1980-08-26 | 1980-08-26 | Burst error correcting system applied to recording device or transmission device of series data byte |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP11641180A JPS5741052A (en) | 1980-08-26 | 1980-08-26 | Burst error correcting system applied to recording device or transmission device of series data byte |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5741052A true JPS5741052A (en) | 1982-03-06 |
Family
ID=14686391
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP11641180A Pending JPS5741052A (en) | 1980-08-26 | 1980-08-26 | Burst error correcting system applied to recording device or transmission device of series data byte |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5741052A (en) |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5965914A (en) * | 1982-10-07 | 1984-04-14 | Sanyo Electric Co Ltd | Error position detecting circuit |
EP0179465A2 (en) * | 1984-10-24 | 1986-04-30 | Nec Corporation | Channel quality monitoring apparatus |
JPS6187279A (en) * | 1984-10-05 | 1986-05-02 | Hitachi Ltd | Decoding circuit |
JPS63281277A (en) * | 1987-05-13 | 1988-11-17 | Hitachi Ltd | Method for correcting crc checking result |
JPH06318324A (en) * | 1994-02-03 | 1994-11-15 | Matsushita Electric Ind Co Ltd | Optical disk reproducing method, recording and reproducing device and address read-out device |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5533278A (en) * | 1978-08-31 | 1980-03-08 | Fujitsu Ltd | Error correcting processor |
JPS5573909A (en) * | 1978-11-28 | 1980-06-04 | Matsushita Electric Ind Co Ltd | Signal processor |
-
1980
- 1980-08-26 JP JP11641180A patent/JPS5741052A/en active Pending
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5533278A (en) * | 1978-08-31 | 1980-03-08 | Fujitsu Ltd | Error correcting processor |
JPS5573909A (en) * | 1978-11-28 | 1980-06-04 | Matsushita Electric Ind Co Ltd | Signal processor |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5965914A (en) * | 1982-10-07 | 1984-04-14 | Sanyo Electric Co Ltd | Error position detecting circuit |
JPS6187279A (en) * | 1984-10-05 | 1986-05-02 | Hitachi Ltd | Decoding circuit |
EP0179465A2 (en) * | 1984-10-24 | 1986-04-30 | Nec Corporation | Channel quality monitoring apparatus |
JPS63281277A (en) * | 1987-05-13 | 1988-11-17 | Hitachi Ltd | Method for correcting crc checking result |
JPH06318324A (en) * | 1994-02-03 | 1994-11-15 | Matsushita Electric Ind Co Ltd | Optical disk reproducing method, recording and reproducing device and address read-out device |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
DE3382661D1 (en) | CORRECTION OF ERROR BUNCHES IN DATA GROUPS. | |
CA2037027A1 (en) | Forward error correction code system | |
ES8205089A1 (en) | Method of error correction | |
EP0092960A3 (en) | Apparatus for checking and correcting digital data | |
JPS5741052A (en) | Burst error correcting system applied to recording device or transmission device of series data byte | |
GB1290023A (en) | ||
JPS5381222A (en) | Digital signal transmitting system | |
JPS5694597A (en) | Memory data control system | |
JPS545416A (en) | Data check system by crc | |
KR970011725B1 (en) | Syndrome circuit for bch decoder | |
JPS51112240A (en) | Input output unit control system | |
JPS5765937A (en) | Split duplex interleave method | |
JPS57100536A (en) | Data buffer device | |
SU962953A1 (en) | Binary code checking device | |
JPS5725046A (en) | Cyclic redundancy check operating circuit | |
RU2007040C1 (en) | Decoder of reed-solomon code | |
JPS55140954A (en) | Block error correcting device | |
GB1018762A (en) | Data transfer system | |
JPS5725048A (en) | Memory error check and control system | |
JPS5762445A (en) | Forecasting parity generation system of register | |
JPS6410341A (en) | Error detecting system | |
JPS51138111A (en) | Data error correction system | |
JPS56149625A (en) | Data transfer control system | |
JPS5619246A (en) | Data transmitting system | |
JPH03104320A (en) | Decoder for burst error correction code |