JPS5739436A - Semiconductor intergrated circuit - Google Patents

Semiconductor intergrated circuit

Info

Publication number
JPS5739436A
JPS5739436A JP55114233A JP11423380A JPS5739436A JP S5739436 A JPS5739436 A JP S5739436A JP 55114233 A JP55114233 A JP 55114233A JP 11423380 A JP11423380 A JP 11423380A JP S5739436 A JPS5739436 A JP S5739436A
Authority
JP
Japan
Prior art keywords
signal
circuit
outputted
clock pulse
processing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP55114233A
Other languages
Japanese (ja)
Inventor
Itsuo Sasaki
Hiroaki Suzuki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP55114233A priority Critical patent/JPS5739436A/en
Publication of JPS5739436A publication Critical patent/JPS5739436A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Power Sources (AREA)
  • Direct Current Feeding And Distribution (AREA)
  • Electric Clocks (AREA)

Abstract

PURPOSE:To obtain an integrated circuit for a clock, which has suppressed power consumption, without exerting influence on the processing operation, by stopping an unnecessary signal until the next processing request is executed after the end of the processing. CONSTITUTION:When processing according to a time counting signal from a frequency divider 2, or processing according to a signal from a key input device has ended, and the circuit is in a state waiting for the next processing request (wait state), a wait signal is outputted from a control part 8. In this case, since the time counting signal or the key input signal is not outputted, a logical ''1'' signal is supplied to an AND circuit 12 from an inverting circuit 14. As a result, the AND circuit 12 is formed, a clock pulse stop signal is outputted, and a clock pulse is not outputted from NOR circuits 4, 5 and a clock pulse generator 7. As a result, operation of the control part 8, an ROM9 and an RAM10 is stopped, and only minimum circuits such as the frequency divider 2, etc. are operated, therefore, the power consumption becomes nearly zero.
JP55114233A 1980-08-20 1980-08-20 Semiconductor intergrated circuit Pending JPS5739436A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55114233A JPS5739436A (en) 1980-08-20 1980-08-20 Semiconductor intergrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55114233A JPS5739436A (en) 1980-08-20 1980-08-20 Semiconductor intergrated circuit

Publications (1)

Publication Number Publication Date
JPS5739436A true JPS5739436A (en) 1982-03-04

Family

ID=14632576

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55114233A Pending JPS5739436A (en) 1980-08-20 1980-08-20 Semiconductor intergrated circuit

Country Status (1)

Country Link
JP (1) JPS5739436A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5979325A (en) * 1982-10-29 1984-05-08 Nec Home Electronics Ltd Power consumption reducing circuit of computer
JPS59200327A (en) * 1983-04-26 1984-11-13 Nec Corp Control system of peripheral device
JPS62111371A (en) * 1985-11-11 1987-05-22 Minolta Camera Co Ltd Storing system for memory sheet
US5548765A (en) * 1990-08-28 1996-08-20 Seiko Epson Corporation Power saving display subsystem for portable computers

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS52149432A (en) * 1976-06-08 1977-12-12 Toshiba Corp Electronic device
JPS5368051A (en) * 1976-11-29 1978-06-17 Sharp Corp Integrated circuit device
JPS53116750A (en) * 1977-03-23 1978-10-12 Citizen Watch Co Ltd Portable electronic unit

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS52149432A (en) * 1976-06-08 1977-12-12 Toshiba Corp Electronic device
JPS5368051A (en) * 1976-11-29 1978-06-17 Sharp Corp Integrated circuit device
JPS53116750A (en) * 1977-03-23 1978-10-12 Citizen Watch Co Ltd Portable electronic unit

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5979325A (en) * 1982-10-29 1984-05-08 Nec Home Electronics Ltd Power consumption reducing circuit of computer
JPS59200327A (en) * 1983-04-26 1984-11-13 Nec Corp Control system of peripheral device
JPH0113573B2 (en) * 1983-04-26 1989-03-07 Nippon Electric Co
JPS62111371A (en) * 1985-11-11 1987-05-22 Minolta Camera Co Ltd Storing system for memory sheet
US5548765A (en) * 1990-08-28 1996-08-20 Seiko Epson Corporation Power saving display subsystem for portable computers

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