JPS5736488A - Memory controller - Google Patents

Memory controller

Info

Publication number
JPS5736488A
JPS5736488A JP11090380A JP11090380A JPS5736488A JP S5736488 A JPS5736488 A JP S5736488A JP 11090380 A JP11090380 A JP 11090380A JP 11090380 A JP11090380 A JP 11090380A JP S5736488 A JPS5736488 A JP S5736488A
Authority
JP
Japan
Prior art keywords
address
write
readout
memory section
counted
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11090380A
Other languages
Japanese (ja)
Inventor
Kazuhiro Iwata
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP11090380A priority Critical patent/JPS5736488A/en
Publication of JPS5736488A publication Critical patent/JPS5736488A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor
    • G06F5/10—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor having a sequence of storage locations each being individually accessible for both enqueue and dequeue operations, e.g. using random access memory

Abstract

PURPOSE:To offer a memory controller in which RAMs can be used as sequential memories even if readout is not made with a given interval or it is faster than the write-in interval. CONSTITUTION:The content of a write-in address pointer 1 is counted up sequentially one by one with a signal applied from a signal line (a) for write-in request to a memory section 4, it is applied to the memory section 4 via a multiplexer 3 as a write-in address, and DATA is written in this address sequentially. For readout request, first the write-in address data is set to a readout address pointer 2, and it is counted up by ''1'' to readout the oldest data stored in the memory section 4 and the data is read out from the memory section 4. Then, the address is counted up every readout.
JP11090380A 1980-08-12 1980-08-12 Memory controller Pending JPS5736488A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11090380A JPS5736488A (en) 1980-08-12 1980-08-12 Memory controller

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11090380A JPS5736488A (en) 1980-08-12 1980-08-12 Memory controller

Publications (1)

Publication Number Publication Date
JPS5736488A true JPS5736488A (en) 1982-02-27

Family

ID=14547584

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11090380A Pending JPS5736488A (en) 1980-08-12 1980-08-12 Memory controller

Country Status (1)

Country Link
JP (1) JPS5736488A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2554952A1 (en) * 1983-11-15 1985-05-17 Telecommunications Sa METHOD AND ADDRESSING SYSTEM FOR DYNAMIC MEMORY
JPH0329179A (en) * 1989-06-26 1991-02-07 Nec Corp Memory circuit device
EP0758770A1 (en) * 1995-08-14 1997-02-19 Deutsche Thomson-Brandt Gmbh Method and circuit for memory control resynchronization

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2554952A1 (en) * 1983-11-15 1985-05-17 Telecommunications Sa METHOD AND ADDRESSING SYSTEM FOR DYNAMIC MEMORY
JPH0329179A (en) * 1989-06-26 1991-02-07 Nec Corp Memory circuit device
EP0758770A1 (en) * 1995-08-14 1997-02-19 Deutsche Thomson-Brandt Gmbh Method and circuit for memory control resynchronization

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