JPS5720952A - Digital signal preproducing device - Google Patents

Digital signal preproducing device

Info

Publication number
JPS5720952A
JPS5720952A JP9484780A JP9484780A JPS5720952A JP S5720952 A JPS5720952 A JP S5720952A JP 9484780 A JP9484780 A JP 9484780A JP 9484780 A JP9484780 A JP 9484780A JP S5720952 A JPS5720952 A JP S5720952A
Authority
JP
Japan
Prior art keywords
signal
digital signal
speed
difference
synchronizing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9484780A
Other languages
Japanese (ja)
Inventor
Takashi Ito
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP9484780A priority Critical patent/JPS5720952A/en
Publication of JPS5720952A publication Critical patent/JPS5720952A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B19/00—Driving, starting, stopping record carriers not specifically of filamentary or web form, or of supports therefor; Control thereof; Control of operating function ; Driving both disc and head
    • G11B19/20—Driving; Starting; Stopping; Control thereof
    • G11B19/24—Arrangements for providing constant relative speed between record carrier and head

Abstract

PURPOSE:To eliminate jitters by counting the 2nd clock signal independent of the 1st clock signal synchronizing with a digital signal and by controlling the transport speed of a recording medium by detecting a difference of the count value. CONSTITUTION:A write address WA from the 1st counter 24 and a read address RA from the 2nd counter 28 are inputted to an error detector 38, which outputs both addresses WA and RA and their difference signal J. This difference signal J is passed through a D/A converter 40 and an amplifier 32 to obtain a signal controlling the turning speed of a motor 12. A servo loop controlling the speed of this motor 12 operates to hold the difference signal between count values WA and RA at a prescribed value, thus keeping the transmission speed of a digital signal A constant. In this constitution, turning-speed control over a disk 10 is exercised on the basis of the bit transmission speed of the digital signal A without depending upon the synchronizing signal of the digital signal A, so jitters due to the detection error, etc., of the synchronizing signal are completely eliminated.
JP9484780A 1980-07-11 1980-07-11 Digital signal preproducing device Pending JPS5720952A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9484780A JPS5720952A (en) 1980-07-11 1980-07-11 Digital signal preproducing device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9484780A JPS5720952A (en) 1980-07-11 1980-07-11 Digital signal preproducing device

Publications (1)

Publication Number Publication Date
JPS5720952A true JPS5720952A (en) 1982-02-03

Family

ID=14121416

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9484780A Pending JPS5720952A (en) 1980-07-11 1980-07-11 Digital signal preproducing device

Country Status (1)

Country Link
JP (1) JPS5720952A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6231068A (en) * 1985-08-02 1987-02-10 Mitsubishi Electric Corp Speed controller for digital signal reproducing device

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS52123212A (en) * 1976-04-09 1977-10-17 Kazuhiro Minamachi System for deleting time distortion of reproduced signal using memory
JPS5497404A (en) * 1978-01-18 1979-08-01 Sharp Corp Buffer memory device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS52123212A (en) * 1976-04-09 1977-10-17 Kazuhiro Minamachi System for deleting time distortion of reproduced signal using memory
JPS5497404A (en) * 1978-01-18 1979-08-01 Sharp Corp Buffer memory device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6231068A (en) * 1985-08-02 1987-02-10 Mitsubishi Electric Corp Speed controller for digital signal reproducing device

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