JPS57207936A - Address setting circuit - Google Patents

Address setting circuit

Info

Publication number
JPS57207936A
JPS57207936A JP56093420A JP9342081A JPS57207936A JP S57207936 A JPS57207936 A JP S57207936A JP 56093420 A JP56093420 A JP 56093420A JP 9342081 A JP9342081 A JP 9342081A JP S57207936 A JPS57207936 A JP S57207936A
Authority
JP
Japan
Prior art keywords
signal
terminal
address
inputted
gate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56093420A
Other languages
Japanese (ja)
Inventor
Yuji Mihara
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP56093420A priority Critical patent/JPS57207936A/en
Publication of JPS57207936A publication Critical patent/JPS57207936A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer And Data Communications (AREA)
  • Communication Control (AREA)
  • Selective Calling Equipment (AREA)

Abstract

PURPOSE:To simplify the circuit constitution and to minimize the size of a terminal device in the address setting system of the terminal device in a data gathering system, by setting and inputting the address set signal synchronously to the clock after the condition signal is set. CONSTITUTION:When an address set signal AD is inputted into a transmission terminal 6 from the master station side or an own terminal after a condition signal S is supplied to a terminal 7, a gate 12 is opened by detecting the start bit ST of the signal AD and outputting a signal C for sampling clock. As the result of this, the address set signal AD is successively inputted from a terminal D of a shift register 14 synchronously to a reference clock BC of a reference clock generating circuit 13. Moreover, a gate controlling circuit 11 counts a prescribed bit number after detecting the start bit ST, and closes a gate 11 whenever it detects a stop bit SP. Therefore, data corresponding to the bit number of the address can be inputted into the shift register 14.
JP56093420A 1981-06-17 1981-06-17 Address setting circuit Pending JPS57207936A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56093420A JPS57207936A (en) 1981-06-17 1981-06-17 Address setting circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56093420A JPS57207936A (en) 1981-06-17 1981-06-17 Address setting circuit

Publications (1)

Publication Number Publication Date
JPS57207936A true JPS57207936A (en) 1982-12-20

Family

ID=14081802

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56093420A Pending JPS57207936A (en) 1981-06-17 1981-06-17 Address setting circuit

Country Status (1)

Country Link
JP (1) JPS57207936A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62181547A (en) * 1985-09-27 1987-08-08 エヌ・ベ−・フイリツプス・フル−イランペンフアブリケン Method and circuit arrangement for generating address for circuit unit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62181547A (en) * 1985-09-27 1987-08-08 エヌ・ベ−・フイリツプス・フル−イランペンフアブリケン Method and circuit arrangement for generating address for circuit unit

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