JPS57204662A - Data communication processing system - Google Patents

Data communication processing system

Info

Publication number
JPS57204662A
JPS57204662A JP8918281A JP8918281A JPS57204662A JP S57204662 A JPS57204662 A JP S57204662A JP 8918281 A JP8918281 A JP 8918281A JP 8918281 A JP8918281 A JP 8918281A JP S57204662 A JPS57204662 A JP S57204662A
Authority
JP
Japan
Prior art keywords
counter
code
generated
signal
signals
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8918281A
Other languages
Japanese (ja)
Inventor
Teruyoshi Mita
Akimasa Yatsuhoshi
Taiho Higuchi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP8918281A priority Critical patent/JPS57204662A/en
Publication of JPS57204662A publication Critical patent/JPS57204662A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L27/00—Modulated-carrier systems
    • H04L27/10—Frequency-modulated carrier systems, i.e. using frequency-shift keying
    • H04L27/14—Demodulator circuits; Receiver circuits
    • H04L27/156—Demodulator circuits; Receiver circuits with demodulation using temporal properties of the received signal, e.g. detecting pulse width
    • H04L27/1563—Demodulator circuits; Receiver circuits with demodulation using temporal properties of the received signal, e.g. detecting pulse width using transition or level detection

Abstract

PURPOSE:To obtain an economical data communication processing system, by demodulating original signals directly from pulse-code-modulated FSK signals without converting them into analog signals once. CONSTITUTION:Signals obtained by pulse-code-modulating FSK waves are set to a register 2 at a time interval which is equal to the sampling cycle, and then, successively transferred to another register 3. Outputs of both the registers 2 and 3 are connected to a decoder 4, and, when the code bit of the registers 3 and 2 is 1 (negative) and 0 (positive), respectively, namely at the zero-crossing point from the negative to the positive, a counter reset signal CR is generated. At any combination of code bits other than the above, a counter step-advancing signal CPU is generated. The counter reset signal CR and the counter step-advancing signal CPU thus generated control a counter 5. The counter output corresponding to the signal cycle is compared with a prescribed value at a comparator 7 and the compared result is sent to a flip flop 8 and outputted as received data RD.
JP8918281A 1981-06-10 1981-06-10 Data communication processing system Pending JPS57204662A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8918281A JPS57204662A (en) 1981-06-10 1981-06-10 Data communication processing system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8918281A JPS57204662A (en) 1981-06-10 1981-06-10 Data communication processing system

Publications (1)

Publication Number Publication Date
JPS57204662A true JPS57204662A (en) 1982-12-15

Family

ID=13963601

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8918281A Pending JPS57204662A (en) 1981-06-10 1981-06-10 Data communication processing system

Country Status (1)

Country Link
JP (1) JPS57204662A (en)

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