JPS57191744A - Terminal controller - Google Patents

Terminal controller

Info

Publication number
JPS57191744A
JPS57191744A JP56076573A JP7657381A JPS57191744A JP S57191744 A JPS57191744 A JP S57191744A JP 56076573 A JP56076573 A JP 56076573A JP 7657381 A JP7657381 A JP 7657381A JP S57191744 A JPS57191744 A JP S57191744A
Authority
JP
Japan
Prior art keywords
central processor
terminals
terminal
flops
flip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56076573A
Other languages
Japanese (ja)
Inventor
Hiroshi Numata
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP56076573A priority Critical patent/JPS57191744A/en
Publication of JPS57191744A publication Critical patent/JPS57191744A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G06F11/0751—Error or fault detection not based on redundancy
    • G06F11/0754—Error or fault detection not based on redundancy by exceeding limits
    • G06F11/076—Error or fault detection not based on redundancy by exceeding limits by exceeding a count or rate limit, e.g. word- or bit count limit

Abstract

PURPOSE:To reduce the load in a central processor, by suppressing the transfer of hard error information from a terminal to the central processor after the number of solid hard errors generated in the terminal reaches a certain number. CONSTITUTION:The number of errors generated in terminals 4-9 is counted by microprocessors 21 of terminal controllers 2-3. Counting values are stored in registers 23; and when they become a certain value, flip-flops 24 provided in respective terminals are set. When these flip-flops 24 are set, the transfer of hard error information from terminals to a central processor 1 is suppressed hereafter. As the result, the load of the central processor 1 is reduced.
JP56076573A 1981-05-22 1981-05-22 Terminal controller Pending JPS57191744A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56076573A JPS57191744A (en) 1981-05-22 1981-05-22 Terminal controller

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56076573A JPS57191744A (en) 1981-05-22 1981-05-22 Terminal controller

Publications (1)

Publication Number Publication Date
JPS57191744A true JPS57191744A (en) 1982-11-25

Family

ID=13608978

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56076573A Pending JPS57191744A (en) 1981-05-22 1981-05-22 Terminal controller

Country Status (1)

Country Link
JP (1) JPS57191744A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63296534A (en) * 1987-05-28 1988-12-02 Nec Corp Directional path establishing system

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63296534A (en) * 1987-05-28 1988-12-02 Nec Corp Directional path establishing system

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