JPS57190413A - Receiver - Google Patents

Receiver

Info

Publication number
JPS57190413A
JPS57190413A JP7521081A JP7521081A JPS57190413A JP S57190413 A JPS57190413 A JP S57190413A JP 7521081 A JP7521081 A JP 7521081A JP 7521081 A JP7521081 A JP 7521081A JP S57190413 A JPS57190413 A JP S57190413A
Authority
JP
Japan
Prior art keywords
output
frequency oscillator
frequency
divider
phase comparator
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP7521081A
Other languages
Japanese (ja)
Other versions
JPS6336688B2 (en
Inventor
Hidemi Ueno
Kiyotake Fukui
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP7521081A priority Critical patent/JPS57190413A/en
Publication of JPS57190413A publication Critical patent/JPS57190413A/en
Publication of JPS6336688B2 publication Critical patent/JPS6336688B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/22—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using more than one loop
    • H03L7/23—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using more than one loop with pulse counters or frequency dividers

Landscapes

  • Channel Selection Circuits, Automatic Tuning Circuits (AREA)

Abstract

PURPOSE:To omit an intermediate-frequency amplifying circuit by detecting input signals with high frequency directly. CONSTITUTION:Frequency oscillated from a variable frequency oscillator 3 is synchronized with the divided frequency from a standard frequency oscillator 8 by the 1st PLL circuit consisting of a divider 7, a phase comparator 5, a low- pass filter 4, and a programmable divider 6. An output of the divider 7 is applied to a phase comparator 10 constituting the 2nd PLL circuit through a divider 9. An output from the 2nd variable frequency oscillator 12 is mixed with an input signal by a mixer 15 and a signal with the frequency corresponding to the difference between the mixed signals is passed through a band-pass filter 16 and applied to one input terminal of a phase comparator 17, which compares said input signal with an output obtained by dividing the output oscillated from the standard frequency oscillator 8 to control the standard frequency oscillator 3 so that its output is completely synchronized with the input signal of phase comparator 17. Consequently, the output of the variable frequency oscillator 3 is completely synchronized with said input signal, which is efficiency detected by a detecting means 1.
JP7521081A 1981-05-18 1981-05-18 Receiver Granted JPS57190413A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7521081A JPS57190413A (en) 1981-05-18 1981-05-18 Receiver

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7521081A JPS57190413A (en) 1981-05-18 1981-05-18 Receiver

Publications (2)

Publication Number Publication Date
JPS57190413A true JPS57190413A (en) 1982-11-24
JPS6336688B2 JPS6336688B2 (en) 1988-07-21

Family

ID=13569601

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7521081A Granted JPS57190413A (en) 1981-05-18 1981-05-18 Receiver

Country Status (1)

Country Link
JP (1) JPS57190413A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0462341A1 (en) * 1989-03-21 1991-12-27 Tft, Inc. A synchronous frequency modulated booster system
FR2673495A1 (en) * 1991-02-28 1992-09-04 Alcatel Telspace FREQUENCY TRANSPOSITION DEVICE WITH AUTOMATIC FREQUENCY CONTROL.

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0462341A1 (en) * 1989-03-21 1991-12-27 Tft, Inc. A synchronous frequency modulated booster system
FR2673495A1 (en) * 1991-02-28 1992-09-04 Alcatel Telspace FREQUENCY TRANSPOSITION DEVICE WITH AUTOMATIC FREQUENCY CONTROL.

Also Published As

Publication number Publication date
JPS6336688B2 (en) 1988-07-21

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