JPS57189243A - Test information transmission system - Google Patents

Test information transmission system

Info

Publication number
JPS57189243A
JPS57189243A JP56074431A JP7443181A JPS57189243A JP S57189243 A JPS57189243 A JP S57189243A JP 56074431 A JP56074431 A JP 56074431A JP 7443181 A JP7443181 A JP 7443181A JP S57189243 A JPS57189243 A JP S57189243A
Authority
JP
Japan
Prior art keywords
circuit
information
signal
synchronizing signal
ffs
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56074431A
Other languages
Japanese (ja)
Inventor
Tetsuro Hirayama
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP56074431A priority Critical patent/JPS57189243A/en
Publication of JPS57189243A publication Critical patent/JPS57189243A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318572—Input/Output interfaces
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318552—Clock circuits details

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)

Abstract

PURPOSE:To use only one test terminal for an integrated circuit, by incorporating a circuit which receives a signal superimposing information and a synchronizing signal, and separates into the information and the synchronizing signal for reproduction, in th integrated circuit. CONSTITUTION:A signal (a) on which information 1, 0, 0 and a synchronizing signal are superimposed is applied to a test input terminal 1 and inputted to a superimposed information separation and reproduction circuit 2 incorporated in an IC circuit. The internal FFs 51-5n of the IC circuit are connected in cascade as a shift register 5. The information (b) separated at the circuit 2 is inputted to a data input 61 of the register 5 and the separated synchronizing signal (c) is given to a clock input 7 of all the FFs 51-5n. The information (b) included in the signal (a) is inputted sequentially to the FFs 51-5n and stored in the shift register 5 for the test of the IC circuit.
JP56074431A 1981-05-18 1981-05-18 Test information transmission system Pending JPS57189243A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56074431A JPS57189243A (en) 1981-05-18 1981-05-18 Test information transmission system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56074431A JPS57189243A (en) 1981-05-18 1981-05-18 Test information transmission system

Publications (1)

Publication Number Publication Date
JPS57189243A true JPS57189243A (en) 1982-11-20

Family

ID=13547015

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56074431A Pending JPS57189243A (en) 1981-05-18 1981-05-18 Test information transmission system

Country Status (1)

Country Link
JP (1) JPS57189243A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4748123A (en) * 1985-06-20 1988-05-31 Celltech Limited Continuous fermentation device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4748123A (en) * 1985-06-20 1988-05-31 Celltech Limited Continuous fermentation device

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