JPS5718094A - Data copying system for duplex memory - Google Patents

Data copying system for duplex memory

Info

Publication number
JPS5718094A
JPS5718094A JP9142880A JP9142880A JPS5718094A JP S5718094 A JPS5718094 A JP S5718094A JP 9142880 A JP9142880 A JP 9142880A JP 9142880 A JP9142880 A JP 9142880A JP S5718094 A JPS5718094 A JP S5718094A
Authority
JP
Japan
Prior art keywords
memory
data
copy
cpu
access request
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP9142880A
Other languages
Japanese (ja)
Other versions
JPS6017137B2 (en
Inventor
Teruaki Takegawa
Akihiko Suzuki
Kenichi Naka
Joichi Futaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panafacom Ltd
Original Assignee
Panafacom Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Panafacom Ltd filed Critical Panafacom Ltd
Priority to JP55091428A priority Critical patent/JPS6017137B2/en
Publication of JPS5718094A publication Critical patent/JPS5718094A/en
Publication of JPS6017137B2 publication Critical patent/JPS6017137B2/en
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/18—Handling requests for interconnection or transfer for access to memory bus based on priority control

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)

Abstract

PURPOSE:To enable data copy without interrupting on-line, by confirming that the duplex memory is not busy and no access request of CPU is present, reading out data from one memory and writing-in it on another. CONSTITUTION:When a duplex memory is operated in data copy mode, the access request from a central processing device is monitored for busy check and the copy for one memory block's share is made only when the access request with the lowest priority is absent. This is done by a priority discrimination circuit 9. The data write- in from the CPU is made both for the normal and correcting systems, and the data readout is made from only the normal system. At the end of all the area copy of memory, it is informed to the CPU through interruption, and if data error impossible of correction is detected 7, the copy is interrupted to inform it to the CPU through interruption.
JP55091428A 1980-07-04 1980-07-04 Duplicated memory data copying method Expired JPS6017137B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55091428A JPS6017137B2 (en) 1980-07-04 1980-07-04 Duplicated memory data copying method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55091428A JPS6017137B2 (en) 1980-07-04 1980-07-04 Duplicated memory data copying method

Publications (2)

Publication Number Publication Date
JPS5718094A true JPS5718094A (en) 1982-01-29
JPS6017137B2 JPS6017137B2 (en) 1985-05-01

Family

ID=14026096

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55091428A Expired JPS6017137B2 (en) 1980-07-04 1980-07-04 Duplicated memory data copying method

Country Status (1)

Country Link
JP (1) JPS6017137B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05120152A (en) * 1991-10-25 1993-05-18 Nec Corp Plural shared memory controller
JPH08137760A (en) * 1994-11-09 1996-05-31 Nec Corp Memory write device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05120152A (en) * 1991-10-25 1993-05-18 Nec Corp Plural shared memory controller
JPH08137760A (en) * 1994-11-09 1996-05-31 Nec Corp Memory write device

Also Published As

Publication number Publication date
JPS6017137B2 (en) 1985-05-01

Similar Documents

Publication Publication Date Title
KR850700171A (en) Access loss processing system and its protection method
DE69901255T2 (en) MULTI-PROCESSOR SYSTEM BRIDGE WITH ACCESS CONTROL
JPS5718094A (en) Data copying system for duplex memory
KR850002914A (en) Message-Oriented Interrupt Devices for Multiprocessor Systems
JPS6153749B2 (en)
JPS5715298A (en) Storage protection system for common memory
EP0626647B1 (en) Copying apparatus for carrying out a copying operation between an active processing system and a stand-by one
JPS57113152A (en) Dumping processing system
JPS5588153A (en) Data processing system
JPS58159129A (en) Dma controller of microcomputer system
JPS5617417A (en) Common bus supervisory system
EP0534665A3 (en) Fault containment system for multiprocessor with shared memory
JPH0256662A (en) Memory protecting system
JPS57186282A (en) Information processing system
JPS5798200A (en) Processing system for memory access fault
JP2776595B2 (en) System control unit
JPH06103222A (en) Bus transfer system
JPS641037A (en) Interrupt driving type information processing system
JPS62251941A (en) Data processor
JPH07152497A (en) Disk control device
JPS5936862A (en) Method of communication between processors
JPS648864B2 (en)
JPS62136171A (en) Facsimile transmission equipment
JPS5712495A (en) Memory control system
JPS56129965A (en) Data transfer control system