JPS57176586A - Method and device for memorizing data - Google Patents

Method and device for memorizing data

Info

Publication number
JPS57176586A
JPS57176586A JP4644282A JP4644282A JPS57176586A JP S57176586 A JPS57176586 A JP S57176586A JP 4644282 A JP4644282 A JP 4644282A JP 4644282 A JP4644282 A JP 4644282A JP S57176586 A JPS57176586 A JP S57176586A
Authority
JP
Japan
Prior art keywords
memorizing data
memorizing
data
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4644282A
Other languages
Japanese (ja)
Inventor
Bitsukuneru Jiyon
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Koninklijke Philips NV
Original Assignee
Philips Gloeilampenfabrieken NV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Philips Gloeilampenfabrieken NV filed Critical Philips Gloeilampenfabrieken NV
Publication of JPS57176586A publication Critical patent/JPS57176586A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor
    • G06F5/065—Partitioned buffers, e.g. allowing multiple independent queues, bidirectional FIFO's

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Controls And Circuits For Display Device (AREA)
  • Memory System (AREA)
JP4644282A 1981-03-25 1982-03-25 Method and device for memorizing data Pending JPS57176586A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
GB8109381A GB2095441A (en) 1981-03-25 1981-03-25 A method of storing data and a store therefor

Publications (1)

Publication Number Publication Date
JPS57176586A true JPS57176586A (en) 1982-10-29

Family

ID=10520655

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4644282A Pending JPS57176586A (en) 1981-03-25 1982-03-25 Method and device for memorizing data

Country Status (5)

Country Link
US (1) US4481576A (en)
EP (1) EP0061804B1 (en)
JP (1) JPS57176586A (en)
DE (1) DE3277473D1 (en)
GB (1) GB2095441A (en)

Families Citing this family (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5287452A (en) * 1990-03-23 1994-02-15 Eastman Kodak Company Bus caching computer display system
EP0473767A1 (en) * 1990-03-23 1992-03-11 Eastman Kodak Company Virtual memory management and allocation arrangement for digital data processing system
US5269009A (en) * 1990-09-04 1993-12-07 International Business Machines Corporation Processor system with improved memory transfer means
DE4127579A1 (en) * 1991-08-21 1993-02-25 Standard Elektrik Lorenz Ag STORAGE UNIT WITH AN ADDRESS GENERATOR
US5666506A (en) * 1994-10-24 1997-09-09 International Business Machines Corporation Apparatus to dynamically control the out-of-order execution of load/store instructions in a processor capable of dispatchng, issuing and executing multiple instructions in a single processor cycle
JP2001256318A (en) * 2000-03-14 2001-09-21 Sony Corp System and method for contents transaction and program providing medium
US6985986B2 (en) 2001-06-01 2006-01-10 Microchip Technology Incorporated Variable cycle interrupt disabling
US7020788B2 (en) 2001-06-01 2006-03-28 Microchip Technology Incorporated Reduced power option
US6552625B2 (en) 2001-06-01 2003-04-22 Microchip Technology Inc. Processor with pulse width modulation generator with fault input prioritization
US6976158B2 (en) 2001-06-01 2005-12-13 Microchip Technology Incorporated Repeat instruction with interrupt
US7467178B2 (en) 2001-06-01 2008-12-16 Microchip Technology Incorporated Dual mode arithmetic saturation processing
US7007172B2 (en) 2001-06-01 2006-02-28 Microchip Technology Incorporated Modified Harvard architecture processor having data memory space mapped to program memory space with erroneous execution protection
US20020184566A1 (en) 2001-06-01 2002-12-05 Michael Catherwood Register pointer trap
US6601160B2 (en) 2001-06-01 2003-07-29 Microchip Technology Incorporated Dynamically reconfigurable data space
US6952711B2 (en) 2001-06-01 2005-10-04 Microchip Technology Incorporated Maximally negative signed fractional number multiplication
US6728856B2 (en) 2001-06-01 2004-04-27 Microchip Technology Incorporated Modified Harvard architecture processor having program memory space mapped to data memory space
US6937084B2 (en) 2001-06-01 2005-08-30 Microchip Technology Incorporated Processor with dual-deadtime pulse width modulation generator
US7003543B2 (en) 2001-06-01 2006-02-21 Microchip Technology Incorporated Sticky z bit
US6934728B2 (en) 2001-06-01 2005-08-23 Microchip Technology Incorporated Euclidean distance instructions
US6604169B2 (en) 2001-06-01 2003-08-05 Microchip Technology Incorporated Modulo addressing based on absolute offset
US6975679B2 (en) 2001-06-01 2005-12-13 Microchip Technology Incorporated Configuration fuses for setting PWM options
US20040021483A1 (en) * 2001-09-28 2004-02-05 Brian Boles Functional pathway configuration at a system/IC interface
US6552567B1 (en) 2001-09-28 2003-04-22 Microchip Technology Incorporated Functional pathway configuration at a system/IC interface

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3571801A (en) * 1966-06-03 1971-03-23 Nasa Data transfer system
JPS5151248A (en) * 1974-10-31 1976-05-06 Fujitsu Ltd Shingotensohoshiki
NL165859C (en) * 1975-04-25 1981-05-15 Philips Nv STATION FOR TRANSFER OF INFORMATION.
US4046995A (en) * 1975-11-17 1977-09-06 Engineered Systems, Inc. Memory fullness indicator
US4383296A (en) * 1980-05-16 1983-05-10 Apple Computer, Inc. Computer with a memory system for remapping a memory having two memory output buses for high resolution display with scrolling of the displayed characters

Also Published As

Publication number Publication date
EP0061804A3 (en) 1985-04-17
EP0061804B1 (en) 1987-10-14
GB2095441A (en) 1982-09-29
EP0061804A2 (en) 1982-10-06
US4481576A (en) 1984-11-06
DE3277473D1 (en) 1987-11-19

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