JPS57170626A - Converting circuit - Google Patents

Converting circuit

Info

Publication number
JPS57170626A
JPS57170626A JP56055834A JP5583481A JPS57170626A JP S57170626 A JPS57170626 A JP S57170626A JP 56055834 A JP56055834 A JP 56055834A JP 5583481 A JP5583481 A JP 5583481A JP S57170626 A JPS57170626 A JP S57170626A
Authority
JP
Japan
Prior art keywords
converter
port
switch
outputted
analog
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56055834A
Other languages
Japanese (ja)
Inventor
Tetsuya Nakamura
Nobushi Yasuura
Makoto Shiozaki
Haruhiko Ogiso
Mitsuhiro Saka
Miya Ishii
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Denso Corp
Original Assignee
NipponDenso Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NipponDenso Co Ltd filed Critical NipponDenso Co Ltd
Priority to JP56055834A priority Critical patent/JPS57170626A/en
Publication of JPS57170626A publication Critical patent/JPS57170626A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03MCODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00Analogue/digital conversion; Digital/analogue conversion
    • H03M1/02Reversible analogue/digital converters

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Microcomputers (AREA)
  • Analogue/Digital Conversion (AREA)

Abstract

PURPOSE:To use parts, which are used for an A/D and a D/A converter, in common and to decrease the number of the parts by using an I/O port, a buffer and a resistance ladder for the D/A converter when they are not used for the A/D converter. CONSTITUTION:This converting circuit normally operates as a D/A converter. In this case, the port 111 of an I/O port 11 has a level LOW, an analog switch 24a is cut off, and an analog switch 24b is closed. Therefore, digital data outputted from the port 11 is passed through a buffer 12 and a resistance ladder to be converted into analog data, which is outputted to a terminal 131 and then applid to an integrating circuit 26 as a sample holding circuit through the switch, so that it is outputted to an analog data output terminal 271 through a voltage follower circuit 27. When a computer requires the analog data, the port 11 is held at a high level to turn the switch 24a on and to turn the switch 24b off. Consequently, the converting circuit operates as an A/D converter.
JP56055834A 1981-04-14 1981-04-14 Converting circuit Pending JPS57170626A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56055834A JPS57170626A (en) 1981-04-14 1981-04-14 Converting circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56055834A JPS57170626A (en) 1981-04-14 1981-04-14 Converting circuit

Publications (1)

Publication Number Publication Date
JPS57170626A true JPS57170626A (en) 1982-10-20

Family

ID=13010003

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56055834A Pending JPS57170626A (en) 1981-04-14 1981-04-14 Converting circuit

Country Status (1)

Country Link
JP (1) JPS57170626A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63199352U (en) * 1987-06-10 1988-12-22
JPH0897721A (en) * 1994-09-28 1996-04-12 Nec Corp Ad/da converter

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63199352U (en) * 1987-06-10 1988-12-22
JPH0897721A (en) * 1994-09-28 1996-04-12 Nec Corp Ad/da converter

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