JPS57157518A - Manufacture of integrated circuit - Google Patents

Manufacture of integrated circuit

Info

Publication number
JPS57157518A
JPS57157518A JP56043306A JP4330681A JPS57157518A JP S57157518 A JPS57157518 A JP S57157518A JP 56043306 A JP56043306 A JP 56043306A JP 4330681 A JP4330681 A JP 4330681A JP S57157518 A JPS57157518 A JP S57157518A
Authority
JP
Japan
Prior art keywords
substrate
converted
processed
mark
informations
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56043306A
Other languages
Japanese (ja)
Inventor
Hisashi Sugiyama
Hirohiko Yamamoto
Susumu Miyazaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP56043306A priority Critical patent/JPS57157518A/en
Publication of JPS57157518A publication Critical patent/JPS57157518A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54493—Peripheral marks on wafers, e.g. orientation flats, notches, lot number
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)

Abstract

PURPOSE:To control the manufacturing condition or process of the IC by converting informations obtained by crossing and scanning the recognition mark of the surface of a semiconductor substrate into digital signals and inputting the signals to a processor. CONSTITUTION:The Si substrate 51 on which the mark 52 of a circle or a similar closed curve is put is encased in a box 53, laser beams 41 are forcussed 42 and introduced onto the surface of the substrate through a fixed reflector 43, a polyhedral rotary mirror 44 and a fixed reflector 45, and the mark is crossed and scanned. Reflected light is detected 47 through a reflector 46, amplified and photoelectric-converted 48, and AD- converted 49. The informations obtained are processed 50, the commands of the manufacturing conditions or processes of separate substrate are emitted, and a laser system is controlled 54. When the width of bars 55, 58 is made double as large as 56 and 57, a space 61 is made double as large as 59 and 60 and the bars are optically scanned, photoelectric-converted and video-processed as the example of the marks, a pulse wave- form is obtained. Signals bit-expressed are octal-processed through AD conversion. According to this method, the substrate need not be positioned accurately, the informations can easily be transmitted to the processor, and the manufacturing process can be automated.
JP56043306A 1981-03-25 1981-03-25 Manufacture of integrated circuit Pending JPS57157518A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56043306A JPS57157518A (en) 1981-03-25 1981-03-25 Manufacture of integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56043306A JPS57157518A (en) 1981-03-25 1981-03-25 Manufacture of integrated circuit

Publications (1)

Publication Number Publication Date
JPS57157518A true JPS57157518A (en) 1982-09-29

Family

ID=12660102

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56043306A Pending JPS57157518A (en) 1981-03-25 1981-03-25 Manufacture of integrated circuit

Country Status (1)

Country Link
JP (1) JPS57157518A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60161614A (en) * 1984-02-02 1985-08-23 Oki Electric Ind Co Ltd Control method of substrate
US5820679A (en) * 1993-07-15 1998-10-13 Hitachi, Ltd. Fabrication system and method having inter-apparatus transporter

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60161614A (en) * 1984-02-02 1985-08-23 Oki Electric Ind Co Ltd Control method of substrate
US5820679A (en) * 1993-07-15 1998-10-13 Hitachi, Ltd. Fabrication system and method having inter-apparatus transporter
US5858863A (en) * 1993-07-15 1999-01-12 Hitachi, Ltd. Fabrication system and method having inter-apparatus transporter
US6099598A (en) * 1993-07-15 2000-08-08 Hitachi, Ltd. Fabrication system and fabrication method
US7062344B2 (en) 1993-07-15 2006-06-13 Renesas Technology Corp. Fabrication system and fabrication method
US7310563B2 (en) 1993-07-15 2007-12-18 Renesas Technology Corp. Fabrication system and fabrication method
US7392106B2 (en) 1993-07-15 2008-06-24 Renesas Technology Corp. Fabrication system and fabrication method
US7603194B2 (en) 1993-07-15 2009-10-13 Renesas Technology Corp. Fabrication system and fabrication method

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