JPS57154613A - Digital modulating system - Google Patents

Digital modulating system

Info

Publication number
JPS57154613A
JPS57154613A JP56040685A JP4068581A JPS57154613A JP S57154613 A JPS57154613 A JP S57154613A JP 56040685 A JP56040685 A JP 56040685A JP 4068581 A JP4068581 A JP 4068581A JP S57154613 A JPS57154613 A JP S57154613A
Authority
JP
Japan
Prior art keywords
pattern
synchronizing signal
circuit
code word
constitution
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56040685A
Other languages
Japanese (ja)
Inventor
Naosaburo Kurita
Tatsuoki Shinohara
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu General Ltd
Aerojet Rocketdyne Holdings Inc
Original Assignee
Fujitsu General Ltd
Gencorp Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu General Ltd, Gencorp Inc filed Critical Fujitsu General Ltd
Priority to JP56040685A priority Critical patent/JPS57154613A/en
Publication of JPS57154613A publication Critical patent/JPS57154613A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
    • G11B20/10—Digital recording or reproducing
    • G11B20/14—Digital recording or reproducing using self-clocking codes
    • G11B20/1403—Digital recording or reproducing using self-clocking codes characterised by the use of two levels
    • G11B20/1423—Code representation depending on subsequent bits, e.g. delay modulation, double density code, Miller code
    • G11B20/1426—Code representation depending on subsequent bits, e.g. delay modulation, double density code, Miller code conversion to or from block codes or representations thereof

Abstract

PURPOSE:To prevent the occurrence of a synchronization error, by using a frame synchronizing signal including a specific pattern in the code word sequence based on the 3PM system to prevent signals, which have the same bit constitution as the synchronizing signal, from existing in data signals. CONSTITUTION:A frame synchronizing signal including pattern 010000 0000000100100 or 0100100000000000100 is used in the code word sequence modulated in the 3PM system. For example, a frame synchronizing signal is used where one bit 0 is added to the head or the tail of one of these patterns. This pattern is generated by a synchronizing pattern generating circuit 10 of a 3PM modulating circuit (a) shown in figure to perform magnetic recording, and this pattern is detected by a synchronizing pattern detecting circuit 13 of a 3PM demodulating circuit (b) to perform decoding and repdoducing.
JP56040685A 1981-03-20 1981-03-20 Digital modulating system Pending JPS57154613A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56040685A JPS57154613A (en) 1981-03-20 1981-03-20 Digital modulating system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56040685A JPS57154613A (en) 1981-03-20 1981-03-20 Digital modulating system

Publications (1)

Publication Number Publication Date
JPS57154613A true JPS57154613A (en) 1982-09-24

Family

ID=12587391

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56040685A Pending JPS57154613A (en) 1981-03-20 1981-03-20 Digital modulating system

Country Status (1)

Country Link
JP (1) JPS57154613A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2558662A1 (en) * 1984-01-24 1985-07-26 Philips Nv METHOD FOR ENCODING A STREAM OF DATA BITS, DEVICE FOR IMPLEMENTING THE METHOD AND DEVICE FOR DECODING THE STREAM OF CHANNEL BITS OBTAINED BY IMPLEMENTING THE PROCESS
JP2009035293A (en) * 2007-08-01 2009-02-19 Sanko Co Ltd Container for transportation

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2558662A1 (en) * 1984-01-24 1985-07-26 Philips Nv METHOD FOR ENCODING A STREAM OF DATA BITS, DEVICE FOR IMPLEMENTING THE METHOD AND DEVICE FOR DECODING THE STREAM OF CHANNEL BITS OBTAINED BY IMPLEMENTING THE PROCESS
JP2009035293A (en) * 2007-08-01 2009-02-19 Sanko Co Ltd Container for transportation

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