JPS57153361A - Processor for logical input and output - Google Patents

Processor for logical input and output

Info

Publication number
JPS57153361A
JPS57153361A JP4016581A JP4016581A JPS57153361A JP S57153361 A JPS57153361 A JP S57153361A JP 4016581 A JP4016581 A JP 4016581A JP 4016581 A JP4016581 A JP 4016581A JP S57153361 A JPS57153361 A JP S57153361A
Authority
JP
Japan
Prior art keywords
output
input
processor
program
logical
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4016581A
Other languages
Japanese (ja)
Inventor
Hisashi Nakama
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP4016581A priority Critical patent/JPS57153361A/en
Publication of JPS57153361A publication Critical patent/JPS57153361A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/44—Arrangements for executing specific programs

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)

Abstract

PURPOSE:To reduce the load required for the processing of logical input and output in a central operation unit, by performing only a logical instruction with a CPU and executing the managing and control execution for input and output with a logical input and output processor. CONSTITUTION:A logical input and output request issued from an application program is transmitted to a logical input and output processor 22 with a program 26. A fundamental application program 23 interpretes the logical input and output request content, produces procedures for physical input and output execution and arranges a required data and given a physical instruction to an input and output execution program 24. This program 24 outputs the content of instruction to an input and output device 25. Since the processor 22 is an entirely independent operation processor form a CPU having an application program 21, a program 26 and a supervisor 27, both can execute independent processing at the same time.
JP4016581A 1981-03-19 1981-03-19 Processor for logical input and output Pending JPS57153361A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4016581A JPS57153361A (en) 1981-03-19 1981-03-19 Processor for logical input and output

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4016581A JPS57153361A (en) 1981-03-19 1981-03-19 Processor for logical input and output

Publications (1)

Publication Number Publication Date
JPS57153361A true JPS57153361A (en) 1982-09-21

Family

ID=12573146

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4016581A Pending JPS57153361A (en) 1981-03-19 1981-03-19 Processor for logical input and output

Country Status (1)

Country Link
JP (1) JPS57153361A (en)

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