JPS57152050A - Switching system of duplex information line - Google Patents

Switching system of duplex information line

Info

Publication number
JPS57152050A
JPS57152050A JP56036388A JP3638881A JPS57152050A JP S57152050 A JPS57152050 A JP S57152050A JP 56036388 A JP56036388 A JP 56036388A JP 3638881 A JP3638881 A JP 3638881A JP S57152050 A JPS57152050 A JP S57152050A
Authority
JP
Japan
Prior art keywords
information line
information
line interface
interruption signal
switching system
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP56036388A
Other languages
Japanese (ja)
Other versions
JPS627581B2 (en
Inventor
Mamiko Nakamura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP56036388A priority Critical patent/JPS57152050A/en
Publication of JPS57152050A publication Critical patent/JPS57152050A/en
Publication of JPS627581B2 publication Critical patent/JPS627581B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring

Abstract

PURPOSE:To exercise control safely over a counter device with a simple program, by transmitting an interruption signal to an inhibiting circuit when one information line is in use and inhibiting the function on another information line. CONSTITUTION:An information line 4 or 4' is used from a CPU1, an interruption signal is given to an inhibition circuit 5' or 5 via an interuption information signal line 6 or 6' to inhibit the use of information line interface 3''' or 3''. In case of reception, the information line interface 3''' or 3'' transmits the interruption signal to the inhibition circuit 5' or 5 via the interference information line 6 or 6' to inhibit the information line interface 3''' or 3''. Thus, since the information line interface 3''' or 3'' is recognized as one, the program is made simple and two information line interfaces can be controlled only with the operation of a control status register 2''.
JP56036388A 1981-03-13 1981-03-13 Switching system of duplex information line Granted JPS57152050A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56036388A JPS57152050A (en) 1981-03-13 1981-03-13 Switching system of duplex information line

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56036388A JPS57152050A (en) 1981-03-13 1981-03-13 Switching system of duplex information line

Publications (2)

Publication Number Publication Date
JPS57152050A true JPS57152050A (en) 1982-09-20
JPS627581B2 JPS627581B2 (en) 1987-02-18

Family

ID=12468462

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56036388A Granted JPS57152050A (en) 1981-03-13 1981-03-13 Switching system of duplex information line

Country Status (1)

Country Link
JP (1) JPS57152050A (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS49115702A (en) * 1973-03-08 1974-11-05
JPS52130543A (en) * 1976-04-27 1977-11-01 Toshiba Corp Multi-computer system

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS49115702A (en) * 1973-03-08 1974-11-05
JPS52130543A (en) * 1976-04-27 1977-11-01 Toshiba Corp Multi-computer system

Also Published As

Publication number Publication date
JPS627581B2 (en) 1987-02-18

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