JPS57150042A - Reading and writing system of instruction - Google Patents

Reading and writing system of instruction

Info

Publication number
JPS57150042A
JPS57150042A JP3478481A JP3478481A JPS57150042A JP S57150042 A JPS57150042 A JP S57150042A JP 3478481 A JP3478481 A JP 3478481A JP 3478481 A JP3478481 A JP 3478481A JP S57150042 A JPS57150042 A JP S57150042A
Authority
JP
Japan
Prior art keywords
instruction
processor
read out
assembler
machine word
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3478481A
Other languages
Japanese (ja)
Inventor
Taiji Nosaka
Hidekiyo Ozawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP3478481A priority Critical patent/JPS57150042A/en
Publication of JPS57150042A publication Critical patent/JPS57150042A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F8/00—Arrangements for software engineering

Abstract

PURPOSE:To facilitate both the discrimination and assembly of a program, by converting a machine word instruction read out of a main body processor into an assembler instruction and displaying it to a service processor to realize an input of an assembler instruction. CONSTITUTION:The communication is carried out between a main body processor 1 and a service processor 3 via a computer console interface line 10. The data read out of the processor 1 is displayed on a display 6. A keyboard 7 is used to supply a data or a command to the processor 3. An adverse converting means 4 converts a machine word instruction of binary display read out of a main storage 2 into an assembler instruction. A converting means 5 converts the assembler instruction supplied from the keyboard 7 into a machine word instruction of binary display.
JP3478481A 1981-03-10 1981-03-10 Reading and writing system of instruction Pending JPS57150042A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3478481A JPS57150042A (en) 1981-03-10 1981-03-10 Reading and writing system of instruction

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3478481A JPS57150042A (en) 1981-03-10 1981-03-10 Reading and writing system of instruction

Publications (1)

Publication Number Publication Date
JPS57150042A true JPS57150042A (en) 1982-09-16

Family

ID=12423898

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3478481A Pending JPS57150042A (en) 1981-03-10 1981-03-10 Reading and writing system of instruction

Country Status (1)

Country Link
JP (1) JPS57150042A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60247738A (en) * 1984-05-22 1985-12-07 Sharp Corp Text editing device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60247738A (en) * 1984-05-22 1985-12-07 Sharp Corp Text editing device

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