JPS57143988A - Reception state detecting circuit of television receiver - Google Patents

Abstract

PURPOSE:To detect an accurate reception state without malfunction by detecting whether a broadcast is received or not by confirming the S-shaped characteristics of an automatic frequency fine adjustment voltage after locking the frequency of a frequency synthesizer PLL circuit. CONSTITUTION:During search channel selection, a coincidence signal between a horizontal signal from a synchronous separating circuit 9 and a flyback pulse from a flayback transformer 12 is supplied to and integrated by a prescribed extent through an integrating circuit 25, whose output is inputted to a controller 21. This controller 21 confirms that a broadcast is received. This confirmation, however, is not completely accurate. For the purpose, when the occurrence of the broadcast reception is confirmed, the frequency division ratio of the programmable divider 16 of a frequency synthesizer PLL circuit B is varies in an increasing and a decreasing direction to vary the lock frequency of a PLL, and an AFT (automatic frequency fine adjustment) voltage from an AFT circuit 8, based upon said variation, is checked to confirm whether it has S-shaped characteristics or not. After this confirmation, the frequency division ratio is returned to the original value and the search channel selection ends.