JPS57143939A - Reception controlling system of superheterodyne receiver - Google Patents
Reception controlling system of superheterodyne receiverInfo
- Publication number
- JPS57143939A JPS57143939A JP56029253A JP2925381A JPS57143939A JP S57143939 A JPS57143939 A JP S57143939A JP 56029253 A JP56029253 A JP 56029253A JP 2925381 A JP2925381 A JP 2925381A JP S57143939 A JPS57143939 A JP S57143939A
- Authority
- JP
- Japan
- Prior art keywords
- time
- synthesizer
- turns
- lock
- switch
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04W—WIRELESS COMMUNICATION NETWORKS
- H04W52/00—Power management, e.g. TPC [Transmission Power Control], power saving or power classes
- H04W52/02—Power saving arrangements
- H04W52/0209—Power saving arrangements in terminal devices
- H04W52/0261—Power saving arrangements in terminal devices managing power supply demand, e.g. depending on battery level
- H04W52/0274—Power saving arrangements in terminal devices managing power supply demand, e.g. depending on battery level by switching on or off the equipment or parts thereof
- H04W52/028—Power saving arrangements in terminal devices managing power supply demand, e.g. depending on battery level by switching on or off the equipment or parts thereof switching on or off only a part of the equipment circuit blocks
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04W—WIRELESS COMMUNICATION NETWORKS
- H04W52/00—Power management, e.g. TPC [Transmission Power Control], power saving or power classes
- H04W52/02—Power saving arrangements
- H04W52/0209—Power saving arrangements in terminal devices
- H04W52/0261—Power saving arrangements in terminal devices managing power supply demand, e.g. depending on battery level
- H04W52/0287—Power saving arrangements in terminal devices managing power supply demand, e.g. depending on battery level changing the clock frequency of a controller in the equipment
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D30/00—Reducing energy consumption in communication networks
- Y02D30/70—Reducing energy consumption in communication networks in wireless communication networks
Abstract
PURPOSE:To secure reception and to reduce power consumption by powering up a phase-locked loop frequency synthesizer for at least a lock-in time perior to other circuits, and by holding its locked state while the circuits are in operation. CONSTITUTION:A power source control circuit 9 turns on a switch 18 intermittently at a prescribed frequency. Consequently, the switch 18 is turned on for the prescribed time W1 and turned off for the remaining time W2. The circuit 19 turns on a switch for a time W3, and turns off it for a time W4. Those switches 18 and 20 are controlled at the same frequency, and a difference between the times W2 and W4 is set equal to or longer than the lock-in time of a phase- locked loop PLL frequency synthesizer 3. Consequently, the synthesizer 3 is powered up at least the lock-in time before circuits 2-11, 15, and 16 other than the synthesizer 3 are powered up.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP56029253A JPS57143939A (en) | 1981-02-27 | 1981-02-27 | Reception controlling system of superheterodyne receiver |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP56029253A JPS57143939A (en) | 1981-02-27 | 1981-02-27 | Reception controlling system of superheterodyne receiver |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS57143939A true JPS57143939A (en) | 1982-09-06 |
Family
ID=12271102
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP56029253A Pending JPS57143939A (en) | 1981-02-27 | 1981-02-27 | Reception controlling system of superheterodyne receiver |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS57143939A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH01265726A (en) * | 1988-04-18 | 1989-10-23 | Sony Corp | Receiver for mobile communication |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS4860809A (en) * | 1971-11-29 | 1973-08-25 | ||
JPS5547742A (en) * | 1978-10-02 | 1980-04-04 | Fujitsu General Ltd | Radio communication unit |
-
1981
- 1981-02-27 JP JP56029253A patent/JPS57143939A/en active Pending
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS4860809A (en) * | 1971-11-29 | 1973-08-25 | ||
JPS5547742A (en) * | 1978-10-02 | 1980-04-04 | Fujitsu General Ltd | Radio communication unit |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH01265726A (en) * | 1988-04-18 | 1989-10-23 | Sony Corp | Receiver for mobile communication |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US4896122A (en) | Multiple bandwidth crystal controlled oscillator | |
FR2711463B1 (en) | ||
JPS5539471A (en) | Electronic device | |
JPS57171845A (en) | Phase locked loop circuit | |
EP0644658A3 (en) | PLL Frequency synthesizer circuit. | |
JPS641330A (en) | Frequency synthesizer | |
EP0355466A3 (en) | Integrated circuit with clock generator circuit | |
JPS57143939A (en) | Reception controlling system of superheterodyne receiver | |
JPS5616988A (en) | Electric power supply unit for bubble memory unit | |
EP0203756A3 (en) | Frequency synthesisers | |
EP0288007A3 (en) | Signal generating apparatus using pll circuit | |
EP0206247A3 (en) | Pll frequency synthesizer | |
JPS57180238A (en) | Reception controlling system for superheterodyne receiver | |
JPS57178434A (en) | Reception controlling ststem of superheterodyne receiver | |
JPH0469459B2 (en) | ||
JPS57180237A (en) | Reception controlling system for superheterodyne receiver | |
JPS64824A (en) | Portable radio equipment with battery saving type channel scanning function | |
JP2750580B2 (en) | Local oscillation method of data receiver | |
JPS56117437A (en) | Pll circuit | |
JPS5776933A (en) | Superheterodyne receiver | |
JPS57170619A (en) | Pll synthesizer tuner | |
JPS5761342A (en) | Pll circuit | |
JPS6462023A (en) | Clock system for semiconductor integrated circuit | |
JPS5249711A (en) | Synthesizer tuner | |
JPS5797234A (en) | Output setting circuit for charge pump |