JPS57142093A - Digital chrominance signal generator - Google Patents
Digital chrominance signal generatorInfo
- Publication number
- JPS57142093A JPS57142093A JP56028234A JP2823481A JPS57142093A JP S57142093 A JPS57142093 A JP S57142093A JP 56028234 A JP56028234 A JP 56028234A JP 2823481 A JP2823481 A JP 2823481A JP S57142093 A JPS57142093 A JP S57142093A
- Authority
- JP
- Japan
- Prior art keywords
- data
- bit
- chrominance
- chrominance signal
- counter
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N11/00—Colour television systems
- H04N11/06—Transmission systems characterised by the manner in which the individual colour picture signal components are combined
- H04N11/18—Transmission systems characterised by the manner in which the individual colour picture signal components are combined using simultaneous and sequential signals, e.g. SECAM-system
- H04N11/186—Decoding means therefor
Abstract
PURPOSE:To reduce the data storage capacity, by storing data to a phase from 0 to 360/(n-1) deg. (where; n is a multiple of chrominance subcarrier frequency) and generating a chrominance signal from 0-360 deg.. CONSTITUTION:A chrominance signal data is stored in a read only memory 51, and a readout address is designated with a data in 9-bit. The 2-bit is a data showing phase (0-89 deg.)-(270-359 deg.), and the remaining 7-bit designates the address corresponding to each phase. Further, the remaining 2-bit is applied to a tetral notation counter 52 to which four times frequency clock pulse Cp of chrominance subcarrier frequency is applied as a preset signal. A load pulse Lp synchronized with the chrominance subcarrier wave is applied to the counter 52 and four operations are given to the chrominance subcarrier wave in the counter 52 and the chrominance signal data of the memory 51 is read in the prescribed other.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP56028234A JPS57142093A (en) | 1981-02-27 | 1981-02-27 | Digital chrominance signal generator |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP56028234A JPS57142093A (en) | 1981-02-27 | 1981-02-27 | Digital chrominance signal generator |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS57142093A true JPS57142093A (en) | 1982-09-02 |
Family
ID=12242898
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP56028234A Pending JPS57142093A (en) | 1981-02-27 | 1981-02-27 | Digital chrominance signal generator |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS57142093A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2647620A1 (en) * | 1989-05-26 | 1990-11-30 | Rca Licensing Corp | PHASE LOCKED SUB-CARRIER REGENERATOR |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS52127740A (en) * | 1976-04-19 | 1977-10-26 | Chubu Nippon Housou Kk | Phase modulating system |
-
1981
- 1981-02-27 JP JP56028234A patent/JPS57142093A/en active Pending
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS52127740A (en) * | 1976-04-19 | 1977-10-26 | Chubu Nippon Housou Kk | Phase modulating system |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2647620A1 (en) * | 1989-05-26 | 1990-11-30 | Rca Licensing Corp | PHASE LOCKED SUB-CARRIER REGENERATOR |
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