JPS57130131A - Multiple computer device - Google Patents

Multiple computer device

Info

Publication number
JPS57130131A
JPS57130131A JP56014588A JP1458881A JPS57130131A JP S57130131 A JPS57130131 A JP S57130131A JP 56014588 A JP56014588 A JP 56014588A JP 1458881 A JP1458881 A JP 1458881A JP S57130131 A JPS57130131 A JP S57130131A
Authority
JP
Japan
Prior art keywords
reset
signal
cps
abnormal
digital
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56014588A
Other languages
Japanese (ja)
Inventor
Fumio Otsuka
Akiro Yoshimi
Manabu Ushida
Yosuke Hamada
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Denso Corp
Original Assignee
NipponDenso Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NipponDenso Co Ltd filed Critical NipponDenso Co Ltd
Priority to JP56014588A priority Critical patent/JPS57130131A/en
Publication of JPS57130131A publication Critical patent/JPS57130131A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Debugging And Monitoring (AREA)
  • Multi Processors (AREA)

Abstract

PURPOSE:To prevent partial or overall malfunctions of the device to improve the reliability, by resetting other digital computers, which are operated in cooperation with an abnormal digital computer, when this digital computer becomes abnormal. CONSTITUTION:The first digital computer CP 1 is connected to an operation panel 3 to control the signal input or th like, and the second digital CP 2 is connected to various input sensors 4 to control an element 5. The CP 2 receives the signal from the CP 1 and gives another signal to the CP 1. When prescribed pulse train signals which CPs 1 and 2 should generate always are broken, the first and the second abnormality reset circuits 6 and 7 judge that CPs 1 and 2 are abnormal to generate the first and the second reset signals of the L level for a constant time. When the reset signal of the L level is generated in one of circiuts 6 and 7 and a power-on reset circuit 6, CPs 1 and 2 are reset together by the action of a logical operation circuit 9.
JP56014588A 1981-02-03 1981-02-03 Multiple computer device Pending JPS57130131A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56014588A JPS57130131A (en) 1981-02-03 1981-02-03 Multiple computer device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56014588A JPS57130131A (en) 1981-02-03 1981-02-03 Multiple computer device

Publications (1)

Publication Number Publication Date
JPS57130131A true JPS57130131A (en) 1982-08-12

Family

ID=11865324

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56014588A Pending JPS57130131A (en) 1981-02-03 1981-02-03 Multiple computer device

Country Status (1)

Country Link
JP (1) JPS57130131A (en)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5843020A (en) * 1981-09-05 1983-03-12 Nippon Telegr & Teleph Corp <Ntt> Resetting circuit of logical device
JPS5979326A (en) * 1982-10-27 1984-05-08 Sanyo Electric Co Ltd Resetting system
JPS608941A (en) * 1983-06-20 1985-01-17 インタ−ナショナル　ビジネス　マシ−ンズ　コ−ポレ−ション Apparatus for maintaining a plurality of processing modules
JPS60231224A (en) * 1984-04-28 1985-11-16 Olympus Optical Co Ltd Reset circuit
JPS6271755U (en) * 1985-10-19 1987-05-08
JPH03222020A (en) * 1990-01-26 1991-10-01 Toshiba Corp Reset system for multi-micro processor system
JP2011107845A (en) * 2009-11-13 2011-06-02 Canon Inc Communication system for electronic equipment

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4828093A (en) * 1971-08-16 1973-04-13
JPS5499540A (en) * 1978-01-23 1979-08-06 Omron Tateisi Electronics Co Malfunction detecting device for electronic circuit
JPS55121566A (en) * 1979-03-12 1980-09-18 Hitachi Ltd Information processor

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4828093A (en) * 1971-08-16 1973-04-13
JPS5499540A (en) * 1978-01-23 1979-08-06 Omron Tateisi Electronics Co Malfunction detecting device for electronic circuit
JPS55121566A (en) * 1979-03-12 1980-09-18 Hitachi Ltd Information processor

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5843020A (en) * 1981-09-05 1983-03-12 Nippon Telegr & Teleph Corp <Ntt> Resetting circuit of logical device
JPH0157810B2 (en) * 1981-09-05 1989-12-07 Nippon Telegraph & Telephone
JPS5979326A (en) * 1982-10-27 1984-05-08 Sanyo Electric Co Ltd Resetting system
JPS608941A (en) * 1983-06-20 1985-01-17 インタ−ナショナル　ビジネス　マシ−ンズ　コ−ポレ−ション Apparatus for maintaining a plurality of processing modules
JPS60231224A (en) * 1984-04-28 1985-11-16 Olympus Optical Co Ltd Reset circuit
JPS6271755U (en) * 1985-10-19 1987-05-08
JPH03222020A (en) * 1990-01-26 1991-10-01 Toshiba Corp Reset system for multi-micro processor system
JP2011107845A (en) * 2009-11-13 2011-06-02 Canon Inc Communication system for electronic equipment

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