JPS57122530A - Photoetching method - Google Patents

Photoetching method

Info

Publication number
JPS57122530A
JPS57122530A JP846581A JP846581A JPS57122530A JP S57122530 A JPS57122530 A JP S57122530A JP 846581 A JP846581 A JP 846581A JP 846581 A JP846581 A JP 846581A JP S57122530 A JPS57122530 A JP S57122530A
Authority
JP
Japan
Prior art keywords
layer
series
substrate
pattern
etched
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP846581A
Other languages
Japanese (ja)
Inventor
Akira Yoshikawa
Akitsu Takeda
Osamu Ochi
Tomoko Kuki
Nobuhiko Mizushima
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP846581A priority Critical patent/JPS57122530A/en
Publication of JPS57122530A publication Critical patent/JPS57122530A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Drying Of Semiconductors (AREA)
  • Weting (AREA)

Abstract

PURPOSE:To obtain a highly accurate pattern by providing a preventive layer made of macromolecular resin material on a singing plate when forming and etching an inorganic photoresist material layer on a substrate, and forming the prescribed pattern from the substrate. CONSTITUTION:When a substrate 3 to be etched made of a semiconductor wafer 1 provided with a metallic layer 2 on the surface is etched, a preventive layer 21 made of an isoprene series, vinyl silicate series or carbolic acid series, which prevents a photo-doping and a reaction with an inorganic resist layer is formed on the surface of the layer 2. Thereafter, an inorganic resist material layer 7 made of a laminate of a selenium series glass material layer 5 and a layer 6 containing silver is covered on the overall surface, accelerated particle beam 8 is emitted in the prescribed pattern to produce a layer 9 doped with silver in the glass. An unexposed part is removed, and the layer 9 is used as a mask layer 10. Subsequently, the exposed layer 21 and then the exposed metallic layer 2 are sequentially etched and removed to obtain a desired metallic layer pattern 11.
JP846581A 1981-01-22 1981-01-22 Photoetching method Pending JPS57122530A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP846581A JPS57122530A (en) 1981-01-22 1981-01-22 Photoetching method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP846581A JPS57122530A (en) 1981-01-22 1981-01-22 Photoetching method

Publications (1)

Publication Number Publication Date
JPS57122530A true JPS57122530A (en) 1982-07-30

Family

ID=11693875

Family Applications (1)

Application Number Title Priority Date Filing Date
JP846581A Pending JPS57122530A (en) 1981-01-22 1981-01-22 Photoetching method

Country Status (1)

Country Link
JP (1) JPS57122530A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60117723A (en) * 1983-11-30 1985-06-25 Fujitsu Ltd Forming method of fine pattern
US6368939B1 (en) * 1997-04-18 2002-04-09 Nec Corporation Multilevel interconnection structure having an air gap between interconnects

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60117723A (en) * 1983-11-30 1985-06-25 Fujitsu Ltd Forming method of fine pattern
JPH0473291B2 (en) * 1983-11-30 1992-11-20 Fujitsu Ltd
US6368939B1 (en) * 1997-04-18 2002-04-09 Nec Corporation Multilevel interconnection structure having an air gap between interconnects

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