JPS57107660A - Communication system - Google Patents

Communication system

Info

Publication number
JPS57107660A
JPS57107660A JP55185789A JP18578980A JPS57107660A JP S57107660 A JPS57107660 A JP S57107660A JP 55185789 A JP55185789 A JP 55185789A JP 18578980 A JP18578980 A JP 18578980A JP S57107660 A JPS57107660 A JP S57107660A
Authority
JP
Japan
Prior art keywords
circuit
switch
signals
signal
filters
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP55185789A
Other languages
Japanese (ja)
Inventor
Masayuki Matsuo
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Electric Works Co Ltd
Original Assignee
Matsushita Electric Works Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Works Ltd filed Critical Matsushita Electric Works Ltd
Priority to JP55185789A priority Critical patent/JPS57107660A/en
Publication of JPS57107660A publication Critical patent/JPS57107660A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L27/00Modulated-carrier systems
    • H04L27/26Systems using multi-frequency codes

Abstract

PURPOSE:To decrease the power consumption, by applying a power supply for a reception processing circuit, only when a modulation frequency signal is detected. CONSTITUTION:A signal consisting of sequential combination of a plurality of modulation frequency signals is received and inputted to a processor 10 through a front end circuit 4, amplifying circuit 5, filters 6-9. The processor 10 interpretes the sequential combination of signals from the filters 6-9, and the output controls a load 3. On the other hand, a signal from an amplifying circuit 5 is discriminated for the level at a level discrimination circuit 11 to detect frequency modulation signals, and a switch drive circuit 12 is activated with this detected output. A switch 14 is inserted between a DC power supply 13 and the processing circuit 10 in interlocking with a switch drive circuit 12, which switches the switch 14.
JP55185789A 1980-12-25 1980-12-25 Communication system Pending JPS57107660A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55185789A JPS57107660A (en) 1980-12-25 1980-12-25 Communication system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55185789A JPS57107660A (en) 1980-12-25 1980-12-25 Communication system

Publications (1)

Publication Number Publication Date
JPS57107660A true JPS57107660A (en) 1982-07-05

Family

ID=16176921

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55185789A Pending JPS57107660A (en) 1980-12-25 1980-12-25 Communication system

Country Status (1)

Country Link
JP (1) JPS57107660A (en)

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