JPS57106050A - Decision of path of wiring pattern - Google Patents

Decision of path of wiring pattern

Info

Publication number
JPS57106050A
JPS57106050A JP55182562A JP18256280A JPS57106050A JP S57106050 A JPS57106050 A JP S57106050A JP 55182562 A JP55182562 A JP 55182562A JP 18256280 A JP18256280 A JP 18256280A JP S57106050 A JPS57106050 A JP S57106050A
Authority
JP
Japan
Prior art keywords
wiring
region
passing point
divided
decided
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP55182562A
Other languages
Japanese (ja)
Other versions
JPH0116013B2 (en
Inventor
Katsuya Sato
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP55182562A priority Critical patent/JPS57106050A/en
Publication of JPS57106050A publication Critical patent/JPS57106050A/en
Publication of JPH0116013B2 publication Critical patent/JPH0116013B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components

Abstract

PURPOSE:To reduce the generating rate of short-circut between patterns by a method wherein the wiring region is divided arbitrarily by straight lines, and the intervals between the patterns passing on the straight lines are made to be dispersed uniformly to the utmost. CONSTITUTION:When the wiring region is to be divided into the regions S, R by the straight lines to form a matrix of mXn, an element Aij=Fsj+Frj+Gj indicates inevitability of that the i-th pattern to occupy the j-th passing point, provided that F is defined as the reciprocal number of expected wiring length in the region when the passing point is j, G is defined as weight of the expected wiring to be obtained from the degree of approach of the end of wiring to the boundary line, and they are regulated as to satisfy the formula. When the x-th passing point is in wiring trouble, it is defined as Aix=0, and when adjoining also is not desired, the value at the neighborhood is also reduced. The wiring region is divided into two by the boundary a-a' by this way, and the passing point Pa whereat the wiring pattern 7-7' to cross the dividing straight line is decided. Then the region is divided into two by the boundary b-b', the passing point Pb is decided, division into two is performed in order to decide the passing point Pi, and when the divided region becomes to have the intended size or less, the wiring pattern 8 in the respective regions can be obtained, and the original wiring pattern 7-7' can be decided.
JP55182562A 1980-12-23 1980-12-23 Decision of path of wiring pattern Granted JPS57106050A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55182562A JPS57106050A (en) 1980-12-23 1980-12-23 Decision of path of wiring pattern

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55182562A JPS57106050A (en) 1980-12-23 1980-12-23 Decision of path of wiring pattern

Publications (2)

Publication Number Publication Date
JPS57106050A true JPS57106050A (en) 1982-07-01
JPH0116013B2 JPH0116013B2 (en) 1989-03-22

Family

ID=16120435

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55182562A Granted JPS57106050A (en) 1980-12-23 1980-12-23 Decision of path of wiring pattern

Country Status (1)

Country Link
JP (1) JPS57106050A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4642890A (en) * 1985-10-31 1987-02-17 At&T Technologies, Inc. Method for routing circuit boards
JPH0338860A (en) * 1989-07-05 1991-02-19 Nec Corp Designing method for wirings of integrated circuit

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4642890A (en) * 1985-10-31 1987-02-17 At&T Technologies, Inc. Method for routing circuit boards
JPH0338860A (en) * 1989-07-05 1991-02-19 Nec Corp Designing method for wirings of integrated circuit

Also Published As

Publication number Publication date
JPH0116013B2 (en) 1989-03-22

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