JPS5710567A - Demodulation circuit for mfm modulation signal - Google Patents

Demodulation circuit for mfm modulation signal

Info

Publication number
JPS5710567A
JPS5710567A JP8566080A JP8566080A JPS5710567A JP S5710567 A JPS5710567 A JP S5710567A JP 8566080 A JP8566080 A JP 8566080A JP 8566080 A JP8566080 A JP 8566080A JP S5710567 A JPS5710567 A JP S5710567A
Authority
JP
Japan
Prior art keywords
pulse
clock pulse
width
detection
window based
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8566080A
Other languages
Japanese (ja)
Inventor
Toshiaki Hioki
Yoshihiko Asano
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sanyo Electric Co Ltd
Original Assignee
Sanyo Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sanyo Electric Co Ltd filed Critical Sanyo Electric Co Ltd
Priority to JP8566080A priority Critical patent/JPS5710567A/en
Publication of JPS5710567A publication Critical patent/JPS5710567A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/38—Synchronous or start-stop systems, e.g. for Baudot code
    • H04L25/40—Transmitting circuits; Receiving circuits
    • H04L25/49—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems
    • H04L25/4904—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems using self-synchronising codes, e.g. split-phase codes

Abstract

PURPOSE:To enable accurate data demodulation by reducing the readout error even if demodulated clock pulse fluctuates slightly, by providing a means to read out the edge detecting pulse extending the width of detection window based on a demodulated clock pulse. CONSTITUTION:Two FF circuits are provided at a ''101'' pattern detecting circuit of a demodulation circuit using a PLL circuit 2 to obtain the ''101'' detection output and a means extending the width detection window based on the demodulated clock pulse is provided. For example, an edge detection pulse (c) via an inverter 8, and a demodulation clock pulse (d) via an inverter 9 are inputted to FF circuits 6, 7 and ''101'' detection output (f) is obtained from an AND gate 10 via the measurement of signal invertion interval and pulse count processing and the pulse width of the output (k) of an AND gate 12 is extended to required width of detection window based on a demodulated clock pulse.
JP8566080A 1980-06-23 1980-06-23 Demodulation circuit for mfm modulation signal Pending JPS5710567A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8566080A JPS5710567A (en) 1980-06-23 1980-06-23 Demodulation circuit for mfm modulation signal

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8566080A JPS5710567A (en) 1980-06-23 1980-06-23 Demodulation circuit for mfm modulation signal

Publications (1)

Publication Number Publication Date
JPS5710567A true JPS5710567A (en) 1982-01-20

Family

ID=13864976

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8566080A Pending JPS5710567A (en) 1980-06-23 1980-06-23 Demodulation circuit for mfm modulation signal

Country Status (1)

Country Link
JP (1) JPS5710567A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP3422626A1 (en) * 2017-06-29 2019-01-02 Analog Devices, Inc. Demodulator for pulse-width modulated clock signals

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4891964A (en) * 1972-03-08 1973-11-29
JPS51131612A (en) * 1975-04-28 1976-11-16 Computer Peripherals Pll decoder for decoding predetermined frequency data signal

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4891964A (en) * 1972-03-08 1973-11-29
JPS51131612A (en) * 1975-04-28 1976-11-16 Computer Peripherals Pll decoder for decoding predetermined frequency data signal

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP3422626A1 (en) * 2017-06-29 2019-01-02 Analog Devices, Inc. Demodulator for pulse-width modulated clock signals
CN109217852A (en) * 2017-06-29 2019-01-15 美国亚德诺半导体公司 Demodulator for pulsewidth modulation clock signal
US10749717B2 (en) 2017-06-29 2020-08-18 Analog Devices, Inc. Demodulator for pulse-width modulated clock signals

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