JPS57105039A - Aligning circuit control system - Google Patents
Aligning circuit control systemInfo
- Publication number
- JPS57105039A JPS57105039A JP55182259A JP18225980A JPS57105039A JP S57105039 A JPS57105039 A JP S57105039A JP 55182259 A JP55182259 A JP 55182259A JP 18225980 A JP18225980 A JP 18225980A JP S57105039 A JPS57105039 A JP S57105039A
- Authority
- JP
- Japan
- Prior art keywords
- aligning
- bus
- gate
- transferred
- data
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
- G06F9/30032—Movement instructions, e.g. MOVE, SHIFT, ROTATE, SHUFFLE
Landscapes
- Engineering & Computer Science (AREA)
- Software Systems (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Executing Machine-Instructions (AREA)
- Complex Calculations (AREA)
Abstract
PURPOSE:To simplify a control and to increase a processing speed of a data, by providing a line address or a row address, and controlling the opening and closing of a bus. CONSTITUTION:On an aligning circuit 2', the respective buses are provided so that a data transferred to each aligning input register AIR-0-AIR-3 can be transferred to one of aligning output registers AOR-0-AOR-3. On each bus, a gate is provided, and the data is transferred by selection and control of this gate. Also, an aligning control part 3 generates a control signal to the gate provided on each bus of the circuit 2'.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP55182259A JPS57105039A (en) | 1980-12-23 | 1980-12-23 | Aligning circuit control system |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP55182259A JPS57105039A (en) | 1980-12-23 | 1980-12-23 | Aligning circuit control system |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS57105039A true JPS57105039A (en) | 1982-06-30 |
JPS6128150B2 JPS6128150B2 (en) | 1986-06-28 |
Family
ID=16115118
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP55182259A Granted JPS57105039A (en) | 1980-12-23 | 1980-12-23 | Aligning circuit control system |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS57105039A (en) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9053640B1 (en) | 1993-12-02 | 2015-06-09 | Adrea, LLC | Interactive electronic book |
-
1980
- 1980-12-23 JP JP55182259A patent/JPS57105039A/en active Granted
Also Published As
Publication number | Publication date |
---|---|
JPS6128150B2 (en) | 1986-06-28 |
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