JPS57104883A - Time controlling system - Google Patents

Time controlling system

Info

Publication number
JPS57104883A
JPS57104883A JP18218980A JP18218980A JPS57104883A JP S57104883 A JPS57104883 A JP S57104883A JP 18218980 A JP18218980 A JP 18218980A JP 18218980 A JP18218980 A JP 18218980A JP S57104883 A JPS57104883 A JP S57104883A
Authority
JP
Japan
Prior art keywords
information processing
time
processing device
time data
processing devices
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP18218980A
Other languages
Japanese (ja)
Other versions
JPS6315607B2 (en
Inventor
Koichi Ono
Hirohisa Fujiki
Ryozo Sakai
Yasuo Ito
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
KDDI Corp
Original Assignee
Fujitsu Ltd
Kokusai Denshin Denwa KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd, Kokusai Denshin Denwa KK filed Critical Fujitsu Ltd
Priority to JP18218980A priority Critical patent/JPS57104883A/en
Publication of JPS57104883A publication Critical patent/JPS57104883A/en
Publication of JPS6315607B2 publication Critical patent/JPS6315607B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G04—HOROLOGY
    • G04G—ELECTRONIC TIME-PIECES
    • G04G7/00—Synchronisation

Abstract

PURPOSE:To set clocks in information processing devices accurately, by interrupting the information processing devices at every specified time by the information processing device having a master clock, and setting the clocks in the other information processing devices. CONSTITUTION:The information processing device M having the master clock MCLK interrupts the information processing devices S at every specified time, and sends the time data of the master clock MCLK to the requesting information processing device S when the request of the readout of the time is received from the information processing device S. The information processing device S synchronizes a built in timer with the interruption. The device starts a specified processing when the time data is sent in response to the request of the time readout, and records the timer value (a) at the time of the time data reception. The difference between the value (a) and the timer value (b) when said processing is finished is obtained. The value obtained by adding the received time data to said difference is set in the clock of the device S.
JP18218980A 1980-12-22 1980-12-22 Time controlling system Granted JPS57104883A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18218980A JPS57104883A (en) 1980-12-22 1980-12-22 Time controlling system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18218980A JPS57104883A (en) 1980-12-22 1980-12-22 Time controlling system

Publications (2)

Publication Number Publication Date
JPS57104883A true JPS57104883A (en) 1982-06-30
JPS6315607B2 JPS6315607B2 (en) 1988-04-05

Family

ID=16113888

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18218980A Granted JPS57104883A (en) 1980-12-22 1980-12-22 Time controlling system

Country Status (1)

Country Link
JP (1) JPS57104883A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4530091A (en) * 1983-07-08 1985-07-16 At&T Bell Laboratories Synchronization of real-time clocks in a packet switching system
JP2011029756A (en) * 2009-07-22 2011-02-10 Mitsubishi Electric Corp Synchronous reference transmission terminal and reception terminal, synchronous reference sending and receiving terminal, synchronization system, and synchronization method

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5599630U (en) * 1978-12-29 1980-07-11

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5599630U (en) * 1978-12-29 1980-07-11

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4530091A (en) * 1983-07-08 1985-07-16 At&T Bell Laboratories Synchronization of real-time clocks in a packet switching system
JP2011029756A (en) * 2009-07-22 2011-02-10 Mitsubishi Electric Corp Synchronous reference transmission terminal and reception terminal, synchronous reference sending and receiving terminal, synchronization system, and synchronization method

Also Published As

Publication number Publication date
JPS6315607B2 (en) 1988-04-05

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